Digital scan-based automatic test pattern generation (ATPG) was recently described for ‘random analog’ circuits with >95% likelihood-weighted coverage of the shorts and opens prescribed by IEEE P2427, with test times99% coverage in <20 µs is possible for DACs that have a binary R-2R and/or unary segment resistor structure, and possibly other structures, with simple design-for-scan-test circuit changes that do not significantly affect performance or area. These DAC types are used in many applications because of their simplicity, speed, and area.

Scan-based automatic test pattern generation (ATPG) is commonly used for ‘random logic’ in ICs, but there is no equivalent for analog/mixed-signal (AMS) circuits due to their diversity of functions, stimuli, and responses. As a result, tests are written manually on the intended automatic test equipment (ATE) with (possibly defective) ‘first silicon’ devices, typically requiring months of effort and test times higher than for the digital circuitry. Proving the defect coverage of these tests in simulation is typically impractical, andth-order filter, bandgap + voltage regulator, 8-bit DAC, and industrial 11-bit SAR ADC achieve comparable or higher coverage of IEEE P2427-specified shorts and opens, relative to specification tests, in <1 ms. Defect coverage can be simulated in <1 hour, fast enough to verify before tape-out.

It has never been practical to simulate production tests of mixed-signal ICs, except for the smallest ones. As a result, tests are written in the language of the intended automatic test equipment (ATE) and debugged on the ATE with (possibly defective) ‘first silicon’ devices – this typically requires months of effort. This paper shows why and how the Procedural Description Language (PDL) defined by IEEE P1687.2 can be used for writing tests that can be simulated before automatically and reliably translating them into ATE code. Examples are provided of automated translation to simulation testbenches that are compatible with manufacturing test limitations, as well as an example translation to (previously) digital-only IEEE 1450 STIL.

Recent papers have proposed methods for more efficient mixed-signal test generation, measuring test stimulus quality, and defect simulation. This paper addresses the most time-consuming remaining step to achieving higher quality mixed-signal ICs: diagnosing defects reported as undetected by an analog fault simulator. A unique method for automatically reporting the observability of each undetected defect is described that works for analog, mixed-signal, and even digital circuits (that don't have scan path access). Results are reported for an 8-bit SAR ADC from the ITC'17 A/MS benchmark circuits, and they reveal that most of the undetected defects can be quickly categorized into those that need a better test stimulus, those that need better output analysis, and those that might need better DFT.

Automotive applications are driving the need for a systematic way to decrease analog test escape rates to 0 DPPM, while providing functional safety. This tutorial briefly reviews the history of analog fault simulation, from academic simulation of basic shorts and opens, to the advent of industrial analog defect/fault simulators. Then it addresses the two biggest problems: no industry-accepted fault model, and impractically long simulation time. The solutions are the proposed IEEE P2427 standard for analog defect coverage, for which a brief summary of its requirements is provided, and a variety of methods to reduce total simulation time, such as defect collapsing, simulating only the most likely defects or likelihood-weighted randomly selection of defects, and parallel simulation.

Automotive applications are driving the need for better IC quality, reliability, and functional safety, in a market that is cost-sensitive and rapidly changing. The goals are to deliver zero defective parts without time-consuming and expensive burn-in, and satisfy functional safety requirements. This paper shows how measuring the percentage of circuit elements that are subject to sufficient stress during testing, especially across thin oxides, can be used as a criterion to drive improving the circuit's reliability. The paper also shows how to more accurately compute a circuit's ISO 26262 metrics using activity-based defect likelihoods. Simulation results are provided for an ITC'17 mixed-signal benchmark circuit (bandgap + LDO + voltage monitor) and for an industrial automotive product IC, showing the potential of the method to improve reliability and functional safety of analog/mixed-signal ICs.

Simulation of defects in industrial analog and mixed-signal (A/MS) circuits has long been regarded as impractical: how to simulate the tens of thousands of potential defects for each test and significant process corner of a PLL or SerDes, for example, when simulating each defect could require hours or days of simulation? Would the results for a subset be useful? This paper shows an efficient flow, consistent with the proposed IEEE P2427 Standard for Analog Defect Modeling and Coverage. The flow describes development of realistic models for hard/catastrophic and soft/parametric defects, introduces analog defect collapsing, discusses coverage results for an ITC'17 A/MS benchmark bandgap voltage reference plus LDO voltage regulator, and a programmable PLL, and shows why the results are applicable to large circuits. The results also show that some strategies are more useful than others.

The percentage of circuit elements stimulated by a test stimulus applied to a mixed-signal circuit is analogous to the toggle coverage of a test pattern applied to a digital circuit and can serve as an estimate of the quality of, or maximum test coverage achievable with, that stimulus. This paper proposes a novel definition for analog activity coverage and how to measure it in a defect-free circuit for any potential defects (shorts, opens, and parametric). Results are provided for the ITC'17 analog benchmark circuits and show that activity coverage is an approximate upper limit for defect coverage. Other uses for measuring test stimulus quality are discussed, such as assessing burn-in and over-voltage stress stimuli, and ensuring defect tolerance measured for ISO 26262 is accurate.

The following topics are dealt with: integrated circuit testing; logic testing; automatic test pattern generation; integrated circuit design; integrated circuit manufacture; logic design; system-on-chip; fault diagnosis; integrated circuit reliability; automatic test equipment.

The ITC'97 analog and mixed-signal (A/MS) benchmark circuits have been available for two decades. This paper discusses why they were useful but not for comparing A/MS design-for-test (DFT) techniques, tests, or fault coverage. First, this paper discusses these and other benchmark circuits, and proposes objectives for better benchmark circuits. The paper then describes the first, publicly-available A/MS benchmark circuits that include realistic process models with corners, SPICE netlists for commonly used A/MS and digital cells, performance specifications, and testbenches. These facilitate publishable comparison of mixed-signal DFT, test, and fault simulation techniques to facilitate improvement for A/MS circuitry, hopefully faster than in the last two decades.

We presented a simple definition for defect tolerance in mixed-signals circuits, along with various defect coverages. These allow defect tolerance techniques to be objectively compared for any type of circuit, using automated analog defect simulation.

By the time volume production test statistics are known, it is usually too late for designers to modify an analog design to improve test cost or coverage, or to add redundancy to improve yield or reliability. Analog fault simulation could provide immediate feedback to designers about the impact of design on production test time, test cost, and test coverage of manufacturing defects, but simulating all such defects is usually not feasible. This paper describes an analog defect simulator developed for industrial mixed-signal circuits. It simulates realistic random defects, and reports likelihood-weighted defect coverage based on user-provided likelihoods for opens, shorts, and excessive variations, and for user-defined defects. An additional benefit of defect simulation is measurement of a circuit's defect tolerance, whether the tolerance is added to improve reliability or yield.

Defect tolerance can improve system reliability and safety, and IC yield. This paper describes metrics for measuring defect tolerance of a mixed-signal circuit block within an IC. A general metric is defined for defect tolerance at the transistor-level, consistent with ISO 26262, and how it can be measured by an analog defect simulator, for digital and mixed-signal circuits, including those that have redundancy, error detection, and/or safe states. In effect, the analog defect simulator automatically implements failure modes and effects analysis (FMEA). It is especially useful for safety-oriented applications, like automotive ICs, but could also be useful for defect tolerance that improves IC yield. Digital and mixed-signal circuit examples illustrate usage.

The process of testing Integrated Circuits involves a huge amount of data: electrical circuit measurements, information from wafer process monitors, spatial location of the dies, wafer lot numbers, etc. In addition, the relationships between faults, process variations and circuit performance are likely to be very complex and non-linear. Test (and its extension to diagnosis) should be considered as a challenging highly dimensional multivariate problem.

Analog simulation is much less efficient than digital simulation, so it is essential to reduce the number of potential defects to be simulated when assessing defect coverage of an analog circuit's test. Simple random sampling (SRS) is a published technique for digital fault sampling; stratified sampling is an improvement explored for analog fault simulation. This paper compares the defect coverage estimation accuracy of several sampling techniques and our improvements based on defect-likelihood-weighted selection, as measured by confidence interval. For practical cases, it is shown that the estimation accuracy of SRS gets progressively worse as defects become less uniform in likelihood, but with weighted selection, accuracy improves. We conclude that defect coverage can always be estimated sufficiently accurately by simulating fewer than a thousand defects (and usually much fewer), regardless of circuit size, analog/digital content, and defect likelihood distribution.

The need for contactless testing of the input/output (I/O) delays in ICs is increasing. Contactless testing facilitates multi-site testing at wafer-sort and final test, known good die (KGD) for 2.5D/3D assemblies, and the use of lower cost ATE. We report results for a 28 nm technology, custom testchip with 2.5 Gb/s I/Os intended for 2.5D assemblies that was specifically designed for characterizing inter-chip delays. The IC has I/O built-in self-test (BIST) with 5~500 picosecond programmable resolution that measures delays via standard boundary scan without changes to the bidirectional I/O circuitry or the boundary scan cells. Based on lessons from the testchip, a modified version of the I/O circuitry was developed that permits measurement of classic ac specifications for I/Os, including data skew, setup/hold time, and data window for signals within the IC or from another IC. The modified I/O circuitry generally reduces I/O delay measurement time by one to two orders of magnitude relative to previously reported results.

The accepted approach in industry today to ensure out-going quality in high-volume manufacturing of analog circuits is to measure datasheet specifications. The lack of a comprehensive fault model that is computationally efficient makes the elimination of any tests or the use of lower-cost alternative tests too risky or too time-consuming. Monte Carlo simulations offer a general way to model parametric variations, but inherently focus on normal instead of defective performance. This paper defines a new, general fault model comprising a set of marginally failing circuit instances to evaluate parametric fault coverage of test suites in a way that reduces the number of Monte Carlo simulations by one or more orders of magnitude. As an illustrative example, the technique is applied to six parameters of an RF low-noise amplifier (LNA).

The accepted approach in industry today to ensure out-going quality in high-volume manufacturing of analog circuits is to directly measure datasheet specifications. To reduce the involved costs it is required to eliminate specification tests or use instead lower-cost alternative tests. However, this is too risky if the resultant fault coverage and yield coverage metrics of the new test approach are not estimated accurately. This paper proposes a methodology to efficiently derive a set of most probable failing and marginally functional circuit instances. Based on this set, we can readily define and estimate fault coverage and yield coverage metrics. Our methodology reduces the required number of Monte Carlo simulations by one or more orders of magnitude. As an illustrative example, the methodology is applied to a radio frequency low-noise amplifier.