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Rouhollah Mousavi Iraei

dblp:145/9309 · also Rouhollah M. Iraei · DBLP profile ↗
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1ranked-venue papers
0as first author
0since 2021 · last 2014
0000-0002-3200-6197ORCID · reported

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 1

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
1 paper
Integrated circuit design · 44% Interconnection networks and networks-on-chip · 44% Emerging computing paradigms · 13%

Topics — the 3 heaviest of 3, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Interconnection networks and networks-on-chip › interconnect architecture
emerging interconnect
0.212014
BEOL Scaling Limits and Next Generation Technology Prospects · DAC 2014
Integrated circuit design
interconnect
0.212014
BEOL Scaling Limits and Next Generation Technology Prospects · DAC 2014
Emerging computing paradigms › spintronics › spintronic computing
all-spin logic
0.112014
BEOL Scaling Limits and Next Generation Technology Prospects · DAC 2014

Methods — techniques the papers use, named apart from their topics

technology scaling analysis · 0.2
YearPublicationVenuePosition
2014 BEOL Scaling Limits and Next Generation Technology Prospects
abstract
This paper presents the major limitations to the interconnect technology scaling at future technology generations and demonstrates both evolutionary and radical potential solutions to the BEOL scaling problem. To address the local interconnect challenges, a novel hybrid Al-Cu interconnect technology is introduced. Performances of carbon-based interconnects are evaluated as a more radical solution. The impact of interconnects and the optimal interconnect options are investigated for emerging next generation devices. Interconnects for new state variables, namely spintronic interconnects, are studied and their potential performances in an all-spin logic system are evaluated.
Azad Naeemi, Ahmet Ceyhan, Vachan Kumar, Chenyun Pan, Rouhollah Mousavi Iraei, Shaloo Rakheja
DAC5