When used for safety-critical applications, embedded systems must behave safely at all times - even in the presence of random hardware faults. To ensure this, fault effect simulation by simulation-based fault injection is an integral part of embedded system development. The high complexity of embedded systems results in low simulation performance if all details of the system are simulated. Not simulating all details, i.e. increasing the simulation abstraction level, speeds up fault injection but can result in less accuracy in predicting the fault impacts on the system behavior. To achieve high accuracy and high simulation performance at the same time, we avoid simulation of details unrelated to the injected fault. For this, we divide the set of faults that can occur in an embedded system into three subsets. For each subset, we select the fault injection abstraction level of the embedded processor model that is as accurate as necessary but as fast as possible. The considered levels are host-compiled simulation, instruction set simulation and register transfer level simulation. For additional speed-up, the abstraction level can be switched during the fault injection simulation between register transfer and instruction set level. The fault set for host-compiled simulation can be reduced by static program analysis. Our results show that adapting the abstraction level to the fault set achieves high performance of the fault injection simulation.

Robustness against errors in hardware must be considered from the very beginning of safety-critical system-on-chip firmware design. Therefore, we present fault injection for test-driven development (TDD) of robust firmware. As TDD is based on instant feedback to the designer, fault injection must execute within few minutes. In contrast to state-of-the-art approaches, we avoid long simulation scenarios and runtimes by injecting faults at the unit level and utilizing host-compiled simulation. Further, three static bit-level analyses of firmware source code and hardware specification reduce the fault set significantly. This accelerates fault injection by several orders of magnitude and enables robustness-aware TDD.

Decreasing device sizes in integrated circuits lead to increasing vulnerability of hardware to errors resulting from radiation, crosstalk or power-supply disturbances. Especially in the automotive domain many tasks of electronics are safety relevant, so that solid error detection and correction is imperative. However, completely safe hardware is too expensive for the cost sensitive automotive market. Hence, software safety mechanisms must deal with errors originating from hardware to ensure safe system behavior. To verify safe system behavior under the influence of hardware errors, fault injection is currently done at integration level, but software redesign at this design stage should be avoided due to high costs. To early detect code vulnerable to hardware errors, we propose fault injection at unit level. Thanks to short simulation scenarios and good parallelization capability, even exhaustive fault injection is possible for multiple representative workloads. Using the results from the fault-injection campaigns, the software designer is able to consider reliability during the implementation phase and avoid costly redesigns.

In today's design of resilient embedded systems, logic circuit components play a key role. Many possible design choices at the gate level, such as implementation architecture or synthesis constraints, are vital for the resilience of the entire system. Hence, EDA algorithms at this level have to support exposing technology characteristics (such as process variations or aging) for consideration on higher levels of abstraction. Similarly, key parameters from system level, such as workload or executed processor instructions, have to be considered at lower levels for accurate analysis of, e.g., degradation effects. Circuit-level timing analysis plays a key role in this context as it provides key metrics such as achievable frequency, available timing margins and timing violation vulnerabilities of the analyzed circuit. We present an enhanced static timing analysis which links technology-level effects to system-level and vice versa. Specifically, we discuss the accurate and efficient consideration of system workload and impact of executed instructions on circuit timing.