Demonstration venue · read-only. Every page can be browsed; the buttons that would change it are switched off. Create an account to run TaxoReview on your own data. A simulation from public publication records: the people listed were not invited and did not agree to review.
? Tutorial for this page

Eunchong Lee

dblp:146/1474 · DBLP profile ↗
← Back
1ranked-venue papers
0as first author
1since 2021 · last 2024
0000-0001-7873-2920ORCID · reported

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 1 · 1 since 2021

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
1 paper
Memory systems · 100%

Topics — the 5 heaviest of 5, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Memory systems
DRAM
0.812024
HAIL-DIMM: Host Access Interleaved with Near-Data Processing on DIMM-based Memory System · DAC 2024
Memory systems › processing-in-memory
near-data processing
0.812024
HAIL-DIMM: Host Access Interleaved with Near-Data Processing on DIMM-based Memory System · DAC 2024
Memory systems
processing-in-memory
0.812024
HAIL-DIMM: Host Access Interleaved with Near-Data Processing on DIMM-based Memory System · DAC 2024
Memory systems › memory architecture
interleaved memory
0.212024
HAIL-DIMM: Host Access Interleaved with Near-Data Processing on DIMM-based Memory System · DAC 2024
Memory systems
memory controller
0.212024
HAIL-DIMM: Host Access Interleaved with Near-Data Processing on DIMM-based Memory System · DAC 2024

Methods — techniques the papers use, named apart from their topics

FPGA prototyping · 0.8
YearPublicationVenuePosition
2024 HAIL-DIMM: Host Access Interleaved with Near-Data Processing on DIMM-based Memory System
abstract
Near-data processing (NDP), a solution to reduce data movement overhead between host and memory, should not interfere with host access to ensure system fairness. We propose a cost-effective and energy-efficient LRDIMM-based NDP architecture (HAIL-DIMM) that can seamlessly interleave NDP and host access and is a drop-in replacement for existing main memory modules. The proposed NDP exploits the interleaving capability of the memory controller to interleave NDP and host access naturally. To take advantage of bank interleaving, an atomic operation of the proposed NDP, which consists of data movement and computation, is recognized by the memory controller as a DDR READ/WRITE but by the HAIL-DIMM as NDP based on the request's address. We implement a prototype of the proposed NDP architecture on an FPGA platform as proof of concept. The evaluation results show that the NDP system achieves up to 2.19x speedup in latency and up to 45.4% energy saving for data movement over the baseline system for memory-bound workloads.
Sang-Seol Lee, Kyungho Kim, Eunchong Lee, Sung-Joon Jang
DAC4