As process geometry shrinks, the complexity of transistors in electrical devices have also increased exponentially. Silicon devices manufactured with these new processes are used in safety-sensitive products. Reliability is, therefore, an extremely important factor in such devices. High quality test and screening are a requirement during production of such devices. In this paper, we present a new methodology for advanced nodes like 3nm that include high quality test patterns to improve screening of defective parts and, scan diagnosis to achieve improved physical failure analysis resolution. In particular, the new scan diagnosis methodology presented in this paper improved defect identification especially in global control signal networks over previous techniques. Experimental results shown in the paper demonstrates the uncovering of real systematic defects that were encountered in silicon production at Samsung Foundry.

Recently, the researches on DNN (deep neural network) using GPUs has been actively conducted. The reason for using GPUs in DNN is that it reduces the learning time by using many computational cores. However, GPUs have no implements to support the reliable computing operations. It can exacerbate the reliability of the deep neural network. To ensure the reliability of the deep neural network, the proposed approach is to utilize the dropout technique used in MLP (Multi-Layer Perceptron) learning. In case of the dropout method, some threads in GPUs do not participate in the calculation and it causes GPUs underutilization. The proposed method uses the GPUs underutilization to support a reliable deep neural network. The proposed approach is available through using the idle neurons with adjacent calculating neurons in the dropout process. The experiment results show that the proposed approach is able to support the reliability issues in GPUs while executing deep neural network algorithms.

Three-dimensional integrated circuits (3-D ICs) are considered to meet the performance needs of future ICs. The core components of 3-D ICs are through-silicon vias (TSVs), which should pass appropriate prebond and post-bond tests in 3-D IC fabrication processes. The test inputs must be injected into the TSVs, and the test results must be extracted. This paper proposes a new test result extraction scheme [fast result extraction by selective shift-out (FRESH)] for prebond and post-bond TSV testing. With additional hardware, the proposed scheme remarkably reduces the TSV test time. FRESH avoids unnecessary test result extraction when the number of faulty TSVs in the TSV set is 0 or exceeds the number of TSV redundancies in the set. These early fault analyses are executed in the checkers of TSV groups. The experimental results show that the proposed scheme can reduce the result extraction time in practical environments.

A new 3-D fuse architecture is proposed to improve the yield of 3-D memories. Because the 2-D memories are stacked to form a 3-D memory, the repair status of the prebond is kept as the good status. However, if faults occur in the postbond on the same cells which were repaired in the prebond, they must be identified and repaired because they cannot be repaired by the previous methods. There is no research on the repair the same faulty cells which occur in the prebond and postbond yet. Therefore, the new 3-D fuse architecture is proposed to repair the faulty cells which occur in the prebond and postbond. The redundancies which repair the faulty cells in the prebond are invalidated. The faulty cells are repaired by other redundancies in the postbond by the proposed 3-D fuse architecture. Thus, the proposed technique can improve the yield of 3-D memories. The experimental results show that the proposed technique can achieve higher yields of 3-D memories because only the proposed technique can repair the same faulty cells occurring in the prebond and postbond, and verify the good repair status of the 3-D memories.

A new built-in self-repair (BISR) scheme is proposed for multiple embedded memories to find optimum point of the performance of BISR for multiple embedded memories. All memories are concurrently tested by the small dedicated built-in self-test to figure out the faulty memories, the number of faults, and irreparability. After all memories are tested, only faulty memories are serially tested and repaired by the shared built-in redundancy analysis according to the sizes of memories in descending order. Thus, the fast test and repair are performed with low area overhead. To accomplish an optimal repair rate and a fast analysis speed, an exhaustive search for all combinations of spare rows and columns is proposed based on the optimized fault collection. Experimental results show that the proposed BISR has the optimal repair rate because of the exhaustive search. The performance of the proposed BISR is located in the optimum point between the test and repair time, and the area overhead. For example, the proposed BISR requires 49.6% of the area and 1.3 times of the test and repair time in comparison with parallel BISR scheme for four memories (one 128 K, two 256 K, and one 512 K memories). Furthermore, the more there are memories, the more superior performance in terms of the test and repair time, and the area overhead is shown.

The 3-D integrated dynamic random-access memory (DRAM) structure with a processor is being widely studied due to advantages, such as a large band-width and data communication power reduction. In these structures, the massive heat generation of the processor results in a high operating temperature and a high refresh rate of the DRAM. Thus, in the 3-D DRAM over processor architecture, temperature-aware refresh management is necessary. However, temperature determination is difficult, because in the 3-D DRAM, the temperature changes dynamically and temperature variation in a DRAM die is complicated. In this paper, a thermal guard-band set-up method for 3-D stacked DRAM is proposed. It considers the latency of the temperature data and the position difference between the temperature sensor and the DRAM cell. With this method, the data reliability of the on-chip temperature sensor-dependent adaptive refresh control is guaranteed. In addition, an efficient temperature sensor built-in and refresh control method is analyzed. The expected refresh power reduction is examined through a simulation.

A 3-dimensional Built-In Self-Repair (3D BISR) scheme is proposed for 3-dimensional (3D) memories. The proposed 3D BISR scheme consists of two phases: a parallel test-repair phase, and a serial test-repair phase. After all memory dice are simultaneously tested, only the faulty memory dice are serially tested and repaired using one Built-In Redundancy Analysis (BIRA) module. Thus, it is a faster test-repair with low area overhead. The proposed BIRA algorithm with a post-share redundancy scheme performs exhaustive searches for all combinations of spare rows and columns. Experimental results show that the proposed 3D BISR is up to two times faster than the 3D serial test-serial repair BISR when seven 2048 × 2048 bit memory dice are stacked. The proposed 3D BISR requires 44.55% of the area in comparison to a 3D parallel test-parallel repair BISR for four stacked memory dice (one 128 K RAM, two 256 K RAMs, and 512 K RAM). The yield of 3D memories is the highest due to the exhaustive search BIRA algorithm with the post-share redundancy scheme as shown in various experimental results.