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Vipin Patel 0001

dblp:148/8896-1 · DBLP profile ↗
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2ranked-venue papers
2as first author
2since 2021 · last 2026
0009-0007-3339-5378ORCID · verified

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 1 · 1 first-author · 1 since 2021Software engineering, systems software and programming languages · 1 · 1 first-author · 1 since 2021

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
1 paper
Memory systems · 100%

Topics — the 4 heaviest of 4, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Memory systems
cache coherence
0.812024
Leveraging Cache Coherence to Detect and Repair False Sharing On-the-fly · MICRO 2024
Memory systems › cache coherence
false sharing
0.812024
Leveraging Cache Coherence to Detect and Repair False Sharing On-the-fly · MICRO 2024
Memory systems › cache coherence
false sharing detection
0.812024
Leveraging Cache Coherence to Detect and Repair False Sharing On-the-fly · MICRO 2024
Memory systems
shared memory
0.812024
Leveraging Cache Coherence to Detect and Repair False Sharing On-the-fly · MICRO 2024

Methods — techniques the papers use, named apart from their topics

simulation · 0.8
YearPublicationVenuePosition
2026 Designing GPU Data Structures for Efficient Memory Oversubscription
abstract
Efficient concurrent data structures are important building blocks for accelerating applications on GPUs. With the ever-increasing memory footprint of GPU workloads, data structures used by kernels can exceed global memory capacity. Using the unified virtual memory (UVM) model is a popular approach for kernels to oversubscribe GPU memory without the need for explicit memory management by a programmer. However, we show that data structures executing with UVM can suffer from performance degradation due to the high overheads associated with data migration and thrashing for irregular access patterns. In this paper, we propose two-level hierarchical designs for hash table and skip list data structures that aim to maximize access locality and handle use cases where the data structure oversubscribes GPU memory. The outer-level container enables efficient jumps to desired regions of the data structure, while the inner container allows operating on the data. The inner container is sized to facilitate efficient data transfers between the CPU and the GPU. Experimental results on a diverse set of input operation sequences show that our data structure designs substantially improve performance over optimized UVM baselines while supporting high degrees of GPU memory oversubscription. Importantly, our proposed design, when used to implement key-value stores in metagenomics classification and k-mer counting applications, achieves a geomean speedup of 2.06× for hash table and 2.37× for skip list over baseline UVM implementations.
Vipin Patel 0001, Srinjoy Sarkar, Swarnendu Biswas, Mainak Chaudhuri
Proc. ACM Program. Lang.1
2024 Leveraging Cache Coherence to Detect and Repair False Sharing On-the-fly
abstract
Performance bugs due to false sharing do not man-ifest as observable correctness errors, and hence are challenging to detect and repair. Prior approaches aim to both detect and repair false sharing instances automatically but most of them suffer from one or more of the following drawbacks: (i) high performance overhead due to expensive tracking of shadow memory, (ii) reliance on imprecise hardware events, and (iii) limited applicability and portability. We present extensions to the MESI cache coherence protocol for efficiently identifying and mitigating false sharing instances. The FSDetect protocol tracks the frequency of coherence misses per cache block to identify harmful instances of falsely shared lines while incurring negligible performance overhead. The FSLite protocol extends FSDetect to transparently privatize the falsely shared lines on accesses after detection, thereby eliminating the performance problem arising from false sharing. FSLite maintains coherence by performing precise byte-level updates of privatized blocks at the LLC on termination of privatization. Our simulation results on a variety of multithreaded workloads show that FSDetect can precisely identify all known harmful instances of false sharing. FSLite, on average, improves the performance of applications suffering from false sharing by 1.39X over the unmodified baseline, at the cost of a minimal increase in the chip area. Furthermore, applications running with FSLite stress the network less and show improved energy behavior.
Vipin Patel 0001, Swarnendu Biswas, Mainak Chaudhuri
MICRO1