Scene classification has become an active research area in remote sensing (RS) image interpretation. Recently, Transformer-based methods have shown great potential in modeling global semantic information and have been exploited in RS scene classification. In this letter, we propose a multi-level fusion Swin Transformer (MFST), which integrates a multi-level feature merging (MFM) module and an adaptive feature compression (AFC) module to further boost the performance for RS scene classification. The MFM module narrows the semantic gaps in multi-level features via patch merging in lower-level feature maps and lateral connections in the top-down pathway. The AFC module makes multi-level features have smaller dimensions and more coherent semantic information by adaptive channel reduction. We evaluate the proposed network on the aerial image dataset (AID) and NWPU-RESISC45 (NWPU) datasets, and the classification results reveal that the proposed network outperforms several state-of-the-art (SOTA) methods.

In practical applications, remote-sensing scene classification tasks generally exhibit data shift problems. In this situation, images have large data discrepancies, leading to diffused features and performance degradation. To address the data shift problem, we propose cosine margin prototypical networks. Specifically, we adopt a cosine margin to constrain strictly features, generating well-clustered and discriminative features. With the cosine margin, our method can alleviate data discrepancies by obtaining discriminative features and further addresses the data shift problem well. We conduct extensive experiments on various datasets and achieve 0.03%–7.11% higher accuracy than existing methods. Competitive experimental results demonstrate that our method can solve the data shift problems well in remote-sensing scene classification.

Currently, remote-sensing (RS) scene classification has played an important role in many practical applications. However, traditional methods that are based on deep convolutional neural networks (DCNNs) have several difficulties when faced with data shift problems: novel classes, varied orientations, and large intraclass variations of RS scene images. In this letter, we propose the rotation-invariant and discriminative-learning prototypical networks (RDPNs) for RS scene classification. RDPN uses A-ORConv32 basic blocks and attention mechanisms to obtain rotation-invariant and discriminative features. In addition, adaptive cosine center loss is proposed to constrain the features to mitigate the large intraclass variations and penalize the hard samples adaptively. We conduct extensive experiments on publicly available datasets and achieve 1.69%–19.38% higher accuracy than existing methods. The experimental results verify that the proposed RDPN can solve the data shift problems well in RS scene classification.

Extensive convolutional neural network (CNN)-based methods have been widely used in remote sensing scene classification. However, the dense operation and huge memory storage of the state-of-the-art models hinder their deployment on low-power embedded devices. In this letter, we propose a mixed-precision quantization method to compress the model size without accuracy degradation. In this method, we propose a symmetric nonlinear quantization scheme to reduce the quantization error. A corresponding three-step training strategy is proposed to improve the performance of the quantized network. Finally, based on the proposed scheme and training strategy, we propose a neural architecture search (NAS)-based quantization bit-width search (NQBS) method. This method can automatically select a bit width for each quantized layer to obtain a mixed-precision network with an optimal model size. We apply the proposed method to the ResNet-34 and SqueezeNet networks and evaluate the quantized networks on the NWPU-RESISC45 data set. The experimental results show that the mixed-precision quantized networks under the proposed method strike a satisfying tradeoff between classification accuracy and model size.

Augment of integration and complexity makes VLSI circuits more sensitive to errors. Also, soft errors caused by Single Event Upset (SEU) have become a significant threat to modern electronic systems. Therefore, the demand of high reliability on modern electronic systems keeps increasing. Aiming at reliability evaluation of fault tolerant very large scale integrated circuits implemented on SRAM-based FPGA, an automated fault injection platform via Internal Configuration Access Port (ICAP) for rapid fault injection is presented in this paper. We adopt a granularly-pipelined fault tolerant CORDIC processor as the Design Under Test (DUT), and a C++ script is deployed for the external fault injection control environment and automating the fault injection procedure. The proposed method can achieve quantities of repeating fault injection tests and is suitable for any fault tolerant design implemented in SRAM-Based FPGA.

To realize real-time imaging for the spaceborne synthetic aperture radar (SAR) using the chirp scaling (CS) algorithm, high generation rates of phase factors and heavy computation loads are unavoidable. For example, updating phase factors continuously in the 2-D time or frequency space is difficult for generating phase factors for real-time imaging. To solve this problem, a modified CS algorithm based on updating phase factors regionally is proposed. Moreover, conventional floating-point arithmetic is unaffordable for real-time imaging onboard. Therefore, fixed-point processing is adopted. In the proposed imaging algorithm, the phase factors are updated only at some specified times and frequencies, and fixed-point operation is adopted. Furthermore, based on the paired echo theory and the finite word length error mathematical model, the effect of the proposed imaging algorithm on the SAR image quality is studied. Moreover, based on the above analysis and the experiments of Chinese HJ-1C and GF-3 spaceborne SAR practical measured data, a hardware system including digital signal processor and field-programmable gate array boards is constructed.

This paper presents the design methodology and implementation of reconfigurable coordinate rotation digital computer (CORDIC) architecture that can be configured to operate in different modes and rotations to achieve singleprecision floating point division, multiplication and square-root operations. Through introducing pre- and post-processing, the float-point operations can be integrated into a unified CORDIC iteration procedure. According to the characteristics of different operations, we propose a pipeline-parallel mixed architecture to optimize the area-delay-efficiency. Finally, the prototype based on Xilinx XC7VX690T has been established to test the performance of the proposed design. The result shows the related error with arithmetic computation is less than 10−6, and the resource-consumption of the proposed design is less than the sum of existing IP cores.

Airplane detection is a challenging problem in complex remote sensing imaging. In this letter, an effective airplane detection framework called Markov random field-fully convolutional network (M-FCN) is proposed. The M-FCN uses a cascade strategy that consists of an FCN-based coarse candidate extraction stage, a multi-Markov random field (multi-MRF)-based region proposal (RP) generation stage, and a final classification stage. In the first stage, the FCN model is trained to be sensitive to airplanes, and a coarse candidate map is generated. This model is scale-, direction-, and color-invariant and does not require many training examples. After the first stage, the coarse candidate map is used as the initial labeling field for a multi-MRF algorithm, and RPs are generated according to the multi-MRF output. This RP-generating strategy can yield more accurate locations with fewer RPs. In the last stage, a convolutional neural network-based classifier is used to improve the precision of the entire framework. Experiments show that the M-FCN has high precision, recall, and location accuracy.

A mixed radix algorithm for the in-place fast Fourier transform (FFT), which is broadly used in most embedded signal processing fields, can be explicitly expressed by an iterative equation based on the Cooley-Tukey algorithm. The expression can be applied to either decimation-in-time (DIT) or decimation-in-frequency (DIF) FFTs with ordered inputs. For many newly emerging low power portable computing applications, such as mobile high definition video compressing, mobile fast and accurate satellite location, etc., the existing methods perform either resource consuming or non-flexible. In this paper, we propose a new addressing scheme for efficiently implementing mixed radix FFTs. In this scheme, we elaborately design an accumulator that can generate accessing addresses for the operands, as well as the twiddle factors. The analytical results show that the proposed scheme reduces the algorithm complexity meanwhile helps the designer to efficiently choose an arbitrary FFT to design the in-place architecture.