This paper addresses the speed bottleneck issue of traditional column-parallel analog-to-digital conversion circuits during the readout process of ultra-large array CMOS image sensors. A high-speed and low-power ADC based on a pipelined/time-to-digital converter hybrid architecture is proposed. This method is based on TDC technology to reduce the parasitic capacitance at the output of the MDAC circuit without compromising the conversion rate of the pipelined architecture, thus achieving a significant reduction in system power consumption. Additionally, the circuit multiplexing technology further enhances the power efficiency of the system. The proposed ADC method has been implemented and verified in a CMOS image sensor chip with an array size of 8192(H)$\times 8192$(V), manufactured with the 55 nm 1P4M CMOS process. Operating at the conditions of a clock frequency of 10 MHz and an input signal range of 1.6 V, the 13-bit ADC achieves a conversion rate of 5 MSPS, an SNDR of 73.82 dB, and an ENOB of 11.97 bits with a power consumption of$214.9~\mu $W. Compared with advanced ADCs, the proposed ADC achieves an optimal FOM1value of 0.011 pJ/step, effectively addressing the design contradiction between power consumption and conversion rate in traditional architectures. This chip achieves a row time of 200 ns and a frame rate of 610 fps with 5.23 W of power consumption.

The combination of lensless diffraction imaging and microfluidics provides a relevant solution for the lab-on-a-chip analysis of cells in the context of the Internet of Medical Things (IoMT). However, the cells are on multiple planes in microfluidics, and they only can be sensed by means of complex algorithms. Taking into account the limited resources available on edge computing, a lightweight multifocal fusion reconstruction algorithm is proposed in this work, which still keeps a high-quality reconstruction. The reconstruction, autofocus, and multifocal fusion are integrated, and the reference light normalization and the object light extraction are achieved to adapt their combination. The integrated process is divided into two stages: the cell diffraction image segmentation and the multifocal fusion, based on mono-focal object light reconstruction and masking, respectively. The single autofocus with the golden section search algorithm is merged into the two stages. Finally, a validation system is built based on an FPGA, with a size of only 45 mm × 45 mm × 75 mm. The average error for 8 μm diameter microspheres is 4.67%. For the white blood cells, the evaluation functions of the criteria, the energy of gradient (EOG), and the variance are improved by 12.2%, 92.3%, and 57.3%, respectively. Under the same accuracy, the global number of searches for focus is reduced by 47%-59%, compared to the two-step golden section method, whereas the global speed is also improved by 53%.

The calculation of division and square root is widely used in edge computing related to image processing, clustering, recognition, and reconstruction, among others. Their common multi-stage serial calculation takes longer, and requires a higher latency, and more redundant hardware resources for multi-dimensional parallel computations. This work proposes a low-latency power series approximate digital computing (PSADIC) paradigm and architecture, which achieves a fast low-latency calculation of multi-dimensional mathematical expressions, focusing on the co-calculation of division and square root. This approach allows to compute not only the division and the square root, but also the inverse and the inverse square root. Moreover, serial and pipelined architectures have been designed here to achieve smaller areas and lower latencies, respectively. Compared to the multi-stage calculation with CORDIC (COordinate Rotation DIgital Computer), the mean relative error distance (MRED) is reduced by 67% in PSADIC. Under TSMC (Taiwan Semiconductor Manufacturing Company) 40nm CMOS technology, the proposed serial and pipelined architectures achieve a 66.67% overall latency reduction compared to the CORDIC when using both its own maximum clock frequency, and a 75% cycle latency reduction. Meanwhile, both the ADP (Area Delay Product) and PDP (Power Delay Product) are also optimized.

The Internet of Medical Things (IoMT) provides great convenience by closely connecting medical devices, doctors, and patients. In health management and disease diagnosis, the development of lensless imaging technology and microfluidics has provided important solutions for implementing the point-of-care testing (POCT) devices used to analyze blood cells. However, the low resolution is one of the significant problems, and the existing work has increased system and algorithmic complexity. We conceived an integrated sense-and-calculate chip for balance and proposed dual-line array subpixel scanning imaging (DL-SSI) for an IoMT-based blood cell acquisition and analysis device. In this article, the line-scan imaging model was derived first, and a background modeling method was proposed to eliminate systematic noise in scanned images. A subpixel displacement estimation method was proposed to calculate the cell’s transient flow velocity based on space-time compensation. The time complexity is reduced by 95.08% at typical value, and it is more friendly to the integrated sense-and-calculate chip in hardware. In the reconstruction and restoration, the interpolation theory of the scanned image was deduced, and both the autofocusing algorithm and phase iteration algorithm was optimized for the scanning reconstructed diffraction image. Finally, a lensless DL-SSI terminal was built for testing, and the theoretical minimum size is 44 mm$\times $44 mm$\times $71.8 mm. Sufficient experiments show that DL-SSI is feasible, effective, and superior for IoMT-based blood cell acquisition and analysis.

This paper presents a hybrid-integrated optical transceiver front-end for beyond-400G short-reach optical links. A pair of the monolithic 8-channel laser drivers and the trans-impedance amplifier (TIA) is developed in 180nm SiGe BiCMOS, incorporating arrayed Vertical-Cavity-Surface- Emitting Lasers and photo-detectors. The driver uses a$2^{\mathrm {nd}}$-order continuous-time linear equalizer (CTLE) to compensate for the channel loss with a nonlinear frequency response. Both the inductive peaking and RC-degeneration are embedded at the output stage to extend the optical modulation bandwidth (BW). The series-peaking and multi-stage distributed CTLE are combined in a resistive feedback TIA topology for improved BW and linearity. Measurement results show up to 100-Gb/s PAM-4 electrical eyes of the driver and TIA. The optical transmitter front-end operates 56 Gb/s, 4.1-dB extinction ratio, and 6.6-pJ/bit power efficiency, while the optical receiver front-end achieves 56-Gb/s,$10^{-6}$bit error rate, and 5.9-pJ/bit power efficiency.

This article presents a reconfigurable silicon- photonics transmitter (TX) for short-reach optical interconnects. The proposed hybrid-integrated TX combines a 65-nm CMOS driver with a 180-nm SOI-CMOS silicon-photonic Mach-Zehnder Modulator (MZM). The driver integrated with in- segment fractional-UI spaced feed-forward equalizer (FFE) is proposed to support the non-return-zero (NRZ) signaling, electrical- and optical-domain 4-level pulse-amplitude modulation (PAM-4) signaling. The driver employs a reconfigurable distributed topology to achieve high swing, wide bandwidth and flexible operation. The MZM is driven differentially in a push-pull configuration for high modulation efficiency. Measurement results show that the proposed TX operates up to 50-Gb/s NRZ data rate with 4-Vppd swing and 1.92-ps RMS jitter. In the optical PAM-4 mode, it reaches 56-Gb/s data rate and achieves >5-dB extinction ratio (ER) at the cost of 10.9-pJ/bit power efficiency.

This brief proposes a wideband interdigital bandpass filter (IBPF), exploiting the through-silicon via (TSV)-based 3-D integrated circuit (3-D IC) technology. IBPF is a structure composed of multiple groups of parallel-coupled line resonators, which can increase the bandwidth and out-band suppression (OBS) characteristics of a bandpass filter. Through the transformation of the Chebyshev low-pass circuit model, a seventh-order IBPF centered at 85 GHz is obtained. By combining TSV technology with the coupling coefficient method, the design process from the Chebyshev low-pass circuit model to the final optimization of IBPF is given. The fractional bandwidth (FBW) of IBPF based on TSV is 63%, the out-of-band suppression is greater than 80 dB, the insertion loss is 1.3 dB, the return loss is 20 dB, and the size of the compact IBPF is only$0.50\times0.34$mm2($0.48\times 0.33\,\,\lambda \text{g}^{2}$).

Simultaneous multithreading (SMT) technology improves CPU throughput, but also causes unpredictable performance fluctuations for co-located workloads. Although recent major SMT processors have adopted some techniques to promote hardware support for quality-of-service (QoS), achieving both precise performance control and high throughput on SMT architectures is still a challenging open problem.

According to the communication channel differences, auxiliary medical devices can be divided into wearable medical devices and implantable medical devices. For wearable medical devices, the channel error rate is analyzed by analogy method. It is found that the logarithmic distribution model is more consistent with the actual situation. Then, based on the analyzing of error generation mechanism, the formula for calculating error rate of implantable medical devices is obtained. The accuracy of the formula is verified by the comparison of simulation and experiment. The biological channel error rate of auxiliary medical devices is analyzed in this paper, which provide a theoretical reference for auxiliary medical devices' clinical application.

A nonlinear single-slope ADC with SOC integrated local contrast stretch using a configurable multi-frequency counter for bio-microfluidic imaging is presented in this paper. Compared with the conventional off-chip global contrast stretching algorithm, this method does not degrade image quality at the interested light intensity range (cell) at the cost of unconsidered range (sheath fluid) and can be integrated into CMOS image sensor directly. Meanwhile, this method provides higher precision of cell image for the later super-resolution reconstruction. The simulation results indicate that more details of cell image can be obtained in this method.

Based on through-silicon-via technology, we propose an ultracompact Butterworth low-pass filter (LPF) with area of 0.01 mm2. An equivalent circuit model of the proposed LPF is exploited, analyzed, and simplified. The comparisons of filtering characteristics among ideal 4-GHz fifth-order Butterworth LPF, equivalent circuit model, and full wave simulation of proposed LPF validate the accuracy of the equivalent circuit model. And the proposed LPF exhibits ultracompact size and superior filtering characteristics compared with the existing LPF.

A self-adaptive output swing adjustment is introduced for the design of energy-efficient 2.5D through-silicon interposer (TSI) I/Os. Instead of transmitting signal with large voltage swing, Q-learning based self-adaptive adjustment is deployed to adjust I/O output-voltage swing under constraints of both power budget and bit error rate (BER). Experimental results show that the adaptive 2.5D TSI I/Os designed in 65nm CMOS can achieve an average of 13mW I/O power, 4GHz bandwidth and 3.25pJ/bit energy efficiency for one channel under 10-6 BER, which has ~21.42% reduction of power and ~14.47% energy efficiency improvement.