Demo Data from VLDB 2026 / reviewers in the wild / expert
Amol Shah 0001
dblp:149/4301-1
· DBLP profile ↗
1ranked-venue papers
0as first author
1since 2021 · last 2026
0009-0008-3476-8364ORCID · verified
Domains — the database's venue-derived domains; a paper can count in several
Systems, architecture and hardware · 1 · 1 since 2021
Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.
| Computer architecture, parallel and distributed computing, and storage systems
1 paper |
Memory systems · 61% Processor architecture and microarchitecture · 30% Parallel and multicore computing · 9% |
Topics — the 4 heaviest of 4, each with the papers that count most for it
| Topic | Weight | Papers | Last | Evidence papers |
|---|---|---|---|---|
Memory systems › processing-in-memory
computing-in-memory |
1.0 | 1 | 2026 | The Memory Processing Unit: A Generalized Interface for End-to-End In-Memory Execution · HPCA 2026 |
Processor architecture and microarchitecture
instruction set architecture |
1.0 | 1 | 2026 | The Memory Processing Unit: A Generalized Interface for End-to-End In-Memory Execution · HPCA 2026 |
Memory systems
processing-in-memory |
1.0 | 1 | 2026 | The Memory Processing Unit: A Generalized Interface for End-to-End In-Memory Execution · HPCA 2026 |
Parallel and multicore computing › parallel computation models
parallel execution models |
0.3 | 1 | 2026 | The Memory Processing Unit: A Generalized Interface for End-to-End In-Memory Execution · HPCA 2026 |
Methods — techniques the papers use, named apart from their topics
microarchitecture-agnostic interface design · 1.0
| Year | Publication | Venue | Position |
|---|---|---|---|
| 2026 | The Memory Processing Unit: A Generalized Interface for End-to-End In-Memory ExecutionabstractThe processing-using-memory (PUM; a.k.a. inmemory computing) paradigm aims to eliminate data movement energy and performance costs by using memory cell interactions to directly perform computation. Given PUM's potential for large savings, prior works have proposed many different datapath microarchitectures to demonstrate how general-purpose PUM benefits a wide range of application kernels. Unfortunately, these efforts largely depend on microarchitecture-specific vector-like interfaces that (1) force many of an application's operations to be offloaded to a CPU, (2) require significant programmer effort to scale up applications to an entire memory chip, and (3) make it impractical to develop badly-needed systems software and programming tools for PUM. To address these three issues, we propose the memory processing unit (MPU), a microarchitecture-agnostic interface layer for general-purpose PUM with three components. First, we develop an MPU instruction set architecture (ISA) with instructions to facilitate application scaling and task coordination. Second, we propose an ensemble execution model that coordinates execution across millions of PUM vector function units and maps to most general-purpose PUM microarchitectures. Third, we design a comprehensive MPU control path that efficiently executes MPU ISA binaries across multiple ensembles, and can enable CPU-free execution of complex end-to-end applications with PUM. We demonstrate how the MPU maps to multiple previously-proposed PUM datapaths, and how it achieves average performance/energy improvements of$\mathbf{1. 7 9} \times \boldsymbol{/} \mathbf{3. 2 3} \times$for$\mathbf{2 1}$data-intensive kernels over these prior works ($67 \times / 47 \times$vs. a modern GPU), while also achieving performance and energy improvements for the complex end-to-end applications. Minh S. Q. Truong, Yiqiu Sun 0002, Dawei Xiong, Amol Shah 0001, Alexander Glass, Abraham Farrell, James A. Bain, L. Richard Carley, Saugata Ghose |
HPCA | 4 |