It is known that graphene nanoribbon (GNR) can be used as interconnects in nano-scale designs. To reduce the manufacturing cost in GNR routing, the constraint on the number of the used layers becomes more important. In this paper, given a set of GNR nets on a constrained set of routing layers inside a limited area, based on the concept of using GNR wires with CNT-via insertion in GNR routing, an efficient routing algorithm can be proposed to maximize the routability of the GNR nets and minimizing the total wirelength in assignment of the feasible routed paths with satisfying the non-crossing constraint on the GNR nets. Firstly, based on the construction of a crossing graph on the length-oriented consideration of the multiple-pin nets, all the intervals representing the GNR nets with covering compatibility can be assigned onto the minimized tracks and the represented intervals on the extra tracks can be reassigned onto the constrained tracks by using two separation-and-reassignment operations. Furthermore, based on the assignment result of the represented intervals on the constrained tracks and the hierarchical covering tree of the independent nets and the separated sub-nets on the constrained layers, the full and partial boundary-oriented paths of the GNR nets can be assigned on the constrained layers for routability and the assigned paths of the GNR nets can be modified to reduce the number of the used bends and the total wirelength of the GNR nets. Compared with the combination of Yen’s routing algorithm and the rip-up and reroute (RAR) process in layer-constrained GNR area routing with CNT-via insertion, the proposed algorithm can increase 2.1% of routability for 12 tested examples under 24 different constraints on the average. In addition, the proposed algorithm can reduce 31.6% of the number of the inserted CNT-vias, 5.5% of the number of the used bends and 2.3% of the total wirelength for 12 tested examples under 13 different constraints with 100% routability on the average.

Good-Die-in-Bad-Neighborhood (GDBN) is a technique employed to identify chips that pass initial tests but may have defects. Previous research used neural networks and expanded observation windows but ignored the impact of isolated dice. This paper improves wafer pattern information through denoising and creates a lightweight model. It also reduces training time by annotating multiple dice simultaneously. Experiments on real-world datasets show the model effectively captures more Test Escapes, reducing Defective Parts Per Million (DPPM) and improving return merchandise authorization gains.

Good-die-in-bad-neighborhood (GDBN) is a widely adopted method utilizing the fact that manufacturing defects tend to exhibit spatial dependency and form a cluster or specific pattern of bad dice on a wafer. Existing research studies on GDBN mainly focus on learning such spatial relationships within a limited observation window through simple mechanisms such as linear regression or multilayer perceptron model. In this paper, we propose MetaFormer-GDBN, a transformer-based deep learning model with the observation window extending to the entire wafer to include broader pattern information. The enhanced neighboring information and model capacity allow our method to capture more complex patterns of bad dice. Experiments show that compared to previous work, our method can achieve up to 50 % performance improvement, reducing the DPPM (defective parts per million) with minimal yield loss.

In semiconductor manufacturing processes, there are several causes of typical defects in silicon wafers, such as operational flaws or equipment malfunctions, which may lead to circuit failure and defective products. Therefore, testing is instrumental in improving overall yield and reliability. GDBN (good die in bad neighborhood) is a widely-used technique of rejecting potentially defective wafers in advance based on the concept that defects tend to cluster together. However, previous studies related to GDBN are limited to a local observation by using a narrow-sighted window and thus ignore the defects patterns of the wafers. In this paper, by leveraging information of wafer defect patterns and extending the observation range to the entire wafer, we strengthen the GDBN method to recognize the potentially defective dice more effectively based on the feature of the different defect patterns. The method proposed in this paper is realized by convolutional neural network technology, and it is also the first method to consider defect patterns of wafers as features to solve the problem of GDBN. Several experiments are conducted on a real-world WM-811K dataset, and the results show that our proposed method not only reduce the cost of return merchandise authorization (RMA) but the DPPM (Defective Parts Per Million) more significantly over other existing methods.

To reduce defect parts per million (DPPM) on IC products, IDDQ testing can be exploited for identifying the outliers which are potentially defective but not detected by sign-off functional and parametric tests. Conventional IDDQ testing paradigms depending on a simple statistical$6\sigma $rule or engineers’ experience are usually too conservative to effectively identify nontrivial outliers, especially, when spatial correlations are of great concern/influence. In article, an improved convolutional neural network (CNN)-based method can be proposed for IDDQ outlier identification. In the proposed method, the mean and the standard deviation on the IDDQ value inside a die under test (DUT) can be predicted by employing a stochastic regression model. According to the predicted mean and standard deviation, we derive an expected IDDQ interval and identify the DUT as an outlier if its actual measured IDDQ value is beyond the expected interval. From the observation of the experimental results, the improved data preprocessing and the improved CNN-based stochastic regression can be contained to enhance the prediction accuracy of the expected IDDQ intervals. In the improved method, the spatial correlations of the neighboring dice inside a window can be considered by training a CNN-based stochastic regression model with a large volume of industrial data on 28 and 65 nm products. The trained model is highly accurate prediction in the$R^{2}$(0.973) and RMSE (0.626 mA) of the expected IDDQ values on 28 nm product and the$R^{2}$(0.942) and RMSE (2.155 uA) of the expected IDDQ values on 65 nm product. Furthermore, the experimental results show that the trained model can capture the potential defective dice by identifying efficient IDDQ outliers.

GDBN (good die in bad neighborhood) methodology has been regarded as an effective technique for reducing DPPM (defect parts per million), by identifying and rejecting suspicious dice even though they test good. Instead of examining eight immediate neighbors or exploiting simple linear regression, in this paper we propose to employ a window of larger size for broad-sighted recognition of neighborhood, and make best use of the larger window for accurate prediction of the suspicious level for any given die. The proposed methodology is realized by using an artificial neural network (NN), and is a breakthrough of NN-based work for solving the problem of GDBN. Various experiments on two sets of data clearly reveal the superiority of our NN-based methodology over other existing methods. Besides reducing DPPM, our methodology is able to achieve 1. 5X-2X better reduction in the cost for return merchandise authorization (RMA).

In order to reduce DPPM (defect parts per million), IDDQ testing methodology can be exploited for identifying "outliers" which are potentially defective but not detected by signoff functional and parametric tests. Conventional IDDQ testing paradigms depending on a simple statistical 6σ rule or engineers’ experience are usually too conservative to effectively identify non-trivial outliers, especially when spatial correlations are of great concern/influence. In this paper, by employing a stochastic regression model, the mean as well as the variance of the IDDQ of a die under test (DUT) can be predicted. According to the predicted mean and variance, we derive an expected IDDQ range and identify the DUT as an outlier if its actual IDDQ measurement is beyond the expected range. The proposed stochastic regression model is obtained by training a convolutional neural network (CNN) and, based on its primitive property of convolutional kernel mapping with large volume of industrial data, spatial correlations (due to spatially-correlated process variations, etc) can be considered/captured. The trained data-driven CNN is highly accurate in terms of R-square (0.958) and RMSE (0.783), and the percentage of identified outliers (0.047%) is very close to the theoretical reference (0.050%), which validates the efficacy of our proposed methodology.

It is well known that single-layer routing is used for RDL routing in flip-chip designs and substrate routing in package designs. In this paper, given a set of two-terminal nets in a single-layer gridded routing plane, the routing regions of all the given nets can be initially constructed. Based on the routing constraints on different intersection conditions of two routing regions in a single layer, the wiring directions of the given nets can be further assigned. Finally, based on the assigned directions of the given nets, the wiring paths of the given nets onto the routing grids can be assigned by diffusing the overlapping paths and eliminating the unnecessary detours in single-layer routing. The experimental results show that our proposed approach can route 99.98% of the given nets in single-layer routing for 6 tested examples in reasonable CPU time on the average.