The power of logarithmic quantizations and computations has been recognized as a useful tool in optimizing the performance of large ML models. In this article, we provide results that demonstrate significantly better quantization signal-to-noise ratio performance thanks to multiple-base logarithmic number systems (MDLNS) in comparison with the floatingpoint quantizations that use the same number of bits. On a hardware level, we present details about our Xilinx VCU-128 FPGA design for dot product and matrixvector computations. The MDLNS matrix-vector design significantly outperforms equivalent fixed-point binary designs in terms of area (A) and time (T) complexity and power consumption as evidenced by a 4× scaling of AT2metric for VLSI performance, and 57% increase in computational throughput per watt compared to fixed-point arithmetic.

A general-purpose analog computing method is proposed to compute the continuous-time solutions of nonlinear partial differential equations (PDEs). The discrete-time difference operator in the standard finite difference time domain (FDTD) method is replaced by continuous-time delay operators that can be realized using analog all-pass filters. The resulting spatially discrete time-continuous (SDTC) update equations are realized using analog circuits which compute continuous-time solutions of the PDE with prescribed initial and boundary conditions. The proposed concept is demonstrated in simulation via an integrated circuit (IC) design of a nonlinear acoustic wave equation solver in 180 nm CMOS technology. Analog arithmetic operations (multiply, scale, and add) are realized in parallel using fully differential op-amps and analog multipliers. The proposed IC computes the PDE solution in parallel at 33 discrete spatial points and has a simulated bandwidth and power consumption of approximately 2 MHz and 3 W, respectively. The performance of the IC is simulated using foundry-supplied device models and quantified using i) the mean squared difference between the circuit simulation results and FDTD simulations, and ii) the noise to signal energy ratio. Acceptable accuracy is obtained, with error metric values varying between -7 and -30 dB for various configurations of the problem. Comparison of the custom analog IC simulations with MATLAB- and C-based FDTD code running on a modern workstation shows an expected average speedup of 205× and 140×, respectively.

This paper describes a single-chip analog computer for solving the one dimensional (1-D) wave equation. The chip integrates a 16-point discrete-time but continuous-valued finite-difference solver with spatially-programmable wave velocity, selectable boundary conditions, and arbitrary input excitation waveforms. Built-in Δ-Σ analog-to-digital converters (ADCs) allow the solution results to be easily read out by a digital processor. The design was realized in TSMC 180 nm CMOS and has an active area of 2.81 mm × 2.64 mm. Experimental results prove the functionality of the proposed analog solver.

A multi-port spatio-temporal noise-shaping ADC is proposed to process plane waves received by spatially-oversampled antenna arrays. In the proposed multi-port ADC, the desired plane waves are processed with a spatial low-pass frequency response whereas the noise and distortion are shaped with a spatial high-pass frequency response. By employing a first-order Butterworth filter, approximately circular passbands and stopbands are achieved for the signal and the noise transfer functions, respectively. The proposed noise-shaping system is designed in the TSMC 180 nm CMOS process, with ADCs and DACs modeled as noise sources. Circuit simulation results show that the proposed system can achieve a bandwidth of 50 MHz.

In this paper, we propose solutions to Maxwell's equations that can be computed using analog computers. Spatially-discrete time-continuous (SDTC) algorithms running on analog computers can be potentially faster and more energy-efficient than fully-discrete numerical solvers. The implementations of fully-discrete partial differential equation (PDE) solvers on high speed digital processors, such as graphics processing units (GPUs), take many clock cycles to compute a single temporal frame of the update equation and thus have relatively low equivalent bandwidths. Our approach is to directly implement temporal recursions in continuous-time by using analog circuits. Such circuits can have bandwidths that greatly exceed the equivalent bandwidths of GPUs. In particular, we propose two analog computing methods that compute the SDTC solutions to Maxwell's equations. In addition to Maxwell's equations, such platforms can be used to accelerate other hard computational problems that involve PDEs derived from continuous-time systems. In continuous-time in Laplace domain (CTLD) method (first approach), the spatial domain partial derivatives in the governing PDE are approximated using discrete finite differences, while applying the Laplace transformation along the time dimension. The resulting spatially-discrete time-continuous update equation is utilized to design an analog circuit that can compute the continuous-time solution. The all-pass delay approximate (APDA) method (second approach) replaces the discrete-time difference operators in the standard finite difference time domain (FDTD) cell (Yee cell) using continuous-time delay operators, which can be realized using analog all-pass filters. Both methods have been simulated using ideal analog circuits in Cadence Spectre for the Dirichlet, Neumann, and radiation boundary conditions. The performance of the proposed methods have been quantified using i) mean squared differences between the results and fully-discrete FDTD simulations, and ii) the noise to signal energy ratio. The CTLD and APDA methods are able to compute the solutions to Maxwell's equations with a noise energy to signal energy ratio γ better than -26 dB and -19 dB, respectively. Both methods have been extended to design analog circuits that compute the continuous-time solution of the 1-D and 2-D wave equations. The CTLD-based 1-D and 2-D analog wave equation solvers are able to compute the solutions with γ better than -72 dB and -60 dB, respectively. The APDA-based 1-D wave equation solver is simulated with a dominant-pole model (which better approximates the non-ideal circuit behavior) along with a propagation delay compensation technique. The non-ideal analog models compute the solution with a difference smaller than -13 dB (in terms of γ). Experimental results from a simplified board-level low-frequency implementation are also presented. The key challenges toward CMOS implementations of the proposed solvers are identified and briefly discussed with possible solutions.

Two continuous-time mathematical computing methods are proposed for solving the multidimensional wave equation leading to realizable analog computing circuits. The proposed analog computing processors will potentially be able to solve a certain special classes of computational problems involving partial differential equations, which are defined from continuous-time systems. The new analog computing methods are first derived and physically implemented for the first-time using low-frequency operational amplifier circuits in order to experimentally verify the correctness of the proposed methods. Both algorithms approximate the spatial domain partial derivatives using discrete finite differences. The first method performs a direct Laplace transform (with respect to the time variable) on the resulting expression. The second method applies the finite difference along the time dimension and then replaces the discrete time difference with a continuous-time delay operator, which in turn, can be realized as an analog all-pass filter. Analog circuit architectures are introduced for different boundary conditions relevant to common electromagnetic simulation problems. A low frequency prototype of the analog wave equation solver (based on method 1) has been designed, realized and tested using board-level operational amplifier circuits. Test results and measurements are provided to demonstrate the wave propagation in the space-time domain.

An analog all-pass filter based transfer function synthesis method is proposed for realizing multifunctional microwave active circuits. An analog realization is obtained by replacing unit sample delays in an existing digital prototype with a second-order all-pass analog filter. A novel space time array processor (STAP) and a frequency and bandwidth agile multi-band filter have been simulated using the proposed transfer function synthesis method using measured S- parameters of a fabricated 130 nm second-order CMOS all- pass filter. Simulated array patterns of the STAP beamformer show improved side-lobe performance for better interference suppression and noise rejection. The tunability of the multi-band analog filter, in terms of the center frequency and the quality factor, is verified up to 8 GHz, which has potential applications in analog microwave front-ends.

RF-FPGAs and field-programmable filter arrays require tunable analog filters that can be digitally reconfigured in real-time to have several user-selected passbands and stopband notches. Such reconfigurable analog filters must operate in the microwave frequencies up to several GHz in order to meet the needs of emerging cognitive radio and reconfigurable radar front-ends. Tunable passive filters based on RF-MEMS, surface acoustic wave- and planar-technologies have been explored in the recent past to achieve this goal. In this paper, a novel RF-IC approach to design microwave filterbanks having multiple bands, each having independently tunable center frequency and quality factors, is proposed. The proposed technique is based on transfer function synthesis using first-order all-pass filters as a building block. Using measured data from a current-mode 130-nm CMOS allpass filter implementation, the feasibility of multi-band tunable filter arrays is simulated with a tuning range of 4 GHz.

Cognitive radio relies on accurate spectrum sensing for increasing the spectral efficiency of wireless networks. A novel array processing scheme is proposed based on a uniform linear array (ULA) of circularly-polarized spiral antennas having frequency range 2–6 GHz, which is used in conjunction with digital beam filters having 2-D IIR transfer functions for accurately and efficiently placing radio sources in wireless environment. Algorithms such as cyclostationary feature extraction is employed at beamformer to measure energy and realize feature/modulation detection, which in turn allows classification of a wireless environment. Simulation examples are provided for demonstrating the low-complexity directional feature detector with applications towards enhancing access to radio spectrum. Examples showing classification of sources by direction, frequency channels and modulation type in the 2–4 GHz band at SNR=6 dB are given.