This paper presents an all digital delay-locked loop (DLL) which achieves low jitter and stable duty cycle correction (DCC) operation. Since the DLL has dual DCC circuit, with the combinations of two DCC circuits, the DLL can correct +12.9% and -6.13% duty error under 2% at 333 MHz with 1.6 V. The DLL operates up to 1.67 GHz with 1.8 V and 1.78 GHz with 2.0 V supply voltage, and its peak-to-peak jitter at 1.4 GHz with 1.8 V is 29 ps. The power dissipations are 4.2 mW (5 mW) at 100 MHz and 19.8 mW (29.5 mW) at 1 GHz with 1.5 V (1.8 V) supply voltage with the help of the update gear circuit from the previous work. And the DLL is fabricated with 54-nm DRAM CMOS technology. The active area of the DLL is 0.11 mm2.

This paper describes a 6 bit 1.25GS/s DAC for WPAN transceivers. The proposed DAC is designed with a current steering segmented 2+4 architecture to achieve low power consumption and a small die area. A master-slave deglitch circuit and regulated cascode current sources are proposed to improve the dynamic performance of the DAC. The DAC, implemented in a 0.18um CMOS technology, shows a SFDR of 49.4dB at the output signal of 551MHz. The prototype DAC consumes 6mW for a Nyquist sinusoidal output signal at a sampling rate of 1.25GHz with the supply voltage of 1.8V. The active area of the chip is 0.0576mm2.

The authors propose a 6-bit 2.5Gsample/s flash-ADC realized in a digital 0.18mum 1-poly 4-metal CMOS technology. To achieve low power with wide analog bandwidth and good performance, the authors employ active interpolation and new comparator latch scheme. The simulation results show that the implemented A/D converter has an effective number of bits (ENOB) of 5.99bit at 224MHz input while consuming 296mW and 5.86bit at 1240MHz input while consuming 341mW operating at 2.5GS/s clock frequency. This corresponds to figure-of-merit numbers (FoM) of 2.36 pJ/convstep at 1240MHz input. The total active area is 0.71mm2.

For obtaining a good tracking performance in an optical disk drive servo system, it is essential to attenuate periodic disturbances caused by eccentric rotation of the disk. This paper proposes a dynamic eccentric error compensation scheme for optical disk drivers to track a periodic reference signal with dynamic change in period. Periodic disturbances can be attenuated using a sinusoidal generator with the known disturbance frequency provided by a motor driver. Optical disk drivers support various speeds. So optical disk drivers have a varying periodic disturbance. To deal with time varying periodic disturbances, a proposed dynamic eccentric error compensation controller is turned based on sinusoidal generator to follow the change of reference period. The sinusoidal generator uses the discrete Fourier transform (DFT) method that models the periodic disturbance. Simulative and experimental results show that the proposed control scheme enables a significant improvement of the tracking accuracy of the radial servomechanism and the random access time.

This paper presents a pointing device using the motion detection algorithm and its system architecture. The proposed motion detection pointing device uses just binary images of the binary CMOS image sensor (BCIS). The binary CMOS image sensor (BCIS) is designed for binary image using new technology. This image sensor detects 30times30 pixel value of the image pattern of the fingerprint. This paper shows how to process for the low power motion detection and to implement the new pointing device for small size and high performance. Since small size and binary images are used for the motion detection, extreme low power consumption and small size are possible. Therefore, this architecture is useful for the mobile applications.

This paper presents an H.264/AVC baseline profile decoder based on a SoC platform design methodology. The overall decoding throughput is increased by optimized software and a dedicated hardware accelerator. We minimize the number of bus accesses and use macroblock (MB) level pipeline processing techniques to achieve a real time operation. We implemented and verified a prototype on a SoC platform with a 32-bit RISC CPU core and FPGA module. Our design can process up to 20 frames/sec with QCIF (176/spl times/144). The proposed architecture can be easily applied to many mobile video application areas such as a digital camera and a DMB (digital multimedia broadcasting) phone.

This paper describes an all digital locked-loop (DLL) with a mixed structure of measure-controlled DLL (MCDLL) and register-controlled DLL (RCDLL). The DLL utilized time to digital converter (TDC) and digital to time converter (DTC) using ring counter for wide range operation with small area, fast lock and duty cycle correction (DCC). Simulation results show lock time less than 40 cycles, 1% duty correction error from 50plusmn10% duty external clock, 12mW power dissipation at 800MHz with a 1.5V supply voltage and a wide locking range from 100MHz to 800MHz in a 0.18mum CMOS technology

This paper presents an H.264/AVC baseline profile decoder based on an SOC platform design methodology. The overall decoding throughput is increased by optimized software and a dedicated hardware accelerator. We minimize the number of bus accesses and use macroblock level pipeline processing techniques to achieve a real time operation. We implemented and verified a prototype on an SOC platform with a 32-bit RISC CPU core and FPGA module. Our design can process up to 30 frames/sec with CIF_(352times288). The proposed architecture can be easily applied to many mobile video application areas such as a digital camera and a DMB (digital multimedia broadcasting) phone

This paper proposes a flexible architecture of the transform processor for multi-CODECs (JPEG, MPEG-2, 4 and H.264). Also the memory control scheme to efficiently store intermediate data is presented. In the proposed architecture, four arrays block process at the same time with 4 parallel process elements and pipelined structure for improving the processing time. For verification, FPGA platform with ARM-9 core is used. The results show that the proposed architecture satisfies the requirements of each CODECS such as JPEG, MPEG-2, 4 and H.264 standard

This paper presents a register controlled delay lock loop (RCDLL) with a time-to-digital converter (TDC) and a new fine delay line (FDL) scheme. The architecture of the proposed DLL uses a time-to-digital converter (TDC), a digital-to-time converter (DTC) scheme for short length of coarse delay line (CDL), and a open loop duty cycle corrector (DCC). While the conventional DLL has two feedback loops, the DLL with an open loop DCC has only one loop. So, it occupies a small area compared to the conventional one. Moreover, new FDL scheme is proposed which is capable of seamless boundary switching with a fixed delay step. HSPICE simulation results are based with ANAM 0.18mum 1P6M CMOS process with 1.5V power supply voltage. Upon the simulation results, the proposed DLL operates correctly from 200MHz to 800MHz. The power consumption is less than 24mW at 800MHz. The active area of the design is 0.178mm2

We have developed dual path all-N logic (DPANL) and applied it to 32-bit adder design for higher performance. The speed is significantly enhanced due to reduced capacitance at each evaluation node of dynamic circuits. The power saving is achieved due to reduced adder cell size and minimal race problem. Post-layout simulation results show that this adder can operate at frequencies up to 1.85 GHz for 0.35-/spl mu/m 1P4M CMOS technology and is 32.4% faster than the adder using all-N transistor (ANT). It also consumes 29.2% less power than the ANT adder. A 0.35-/spl mu/m CMOS chip has been fabricated and tested to verify the functionality and performance of the DPANL adder on silicon.

Transient noise simulations are beneficial to design analog circuits, such as peak detection circuits for detecting very small signal levels, or circuits having large gains to be saturated by noise signals. Though the noise characteristics of these circuits can be simulated with SPICE in frequency domain, the dynamic noise performance cannot be shown with noise analysis in frequency domain. The transient noise model for white noise such as thermal noise of the resistor can be generated in time domain with Gaussian distributed random numbers, because the white noise is independent of frequency. But the transient noise model for frequency-dependent noise sources such as 1/f noise is hard to generate in the time domain. In this paper, a transient noise model for frequency-dependent noise sources is presented, and its application is shown.

A one-chip integrated circuit of a 2 W class-D audio power amplifier with very high efficiency using CMOS technology is presented in this paper. Compared with traditional class-AB amplifiers that are very poor at efficiency, mostly below 50%, the proposed amplifier has an efficiency of 90% at a smaller distortion level. Conventional class-D amplifiers generate pulse-width-modulated (PWM) signals by comparing a triangle-wave with input-signals. The proposed class-D amplifier generates signals by a delta-sigma modulation scheme for smaller chip area and simpler application circuits. This amplifier is implemented in a 0.65 /spl mu/m double-metal, double-poly process and occupies 3.5 mm/spl times/3.5 mm.