A new fault simulator (VFSIM) for synchronous sequential circuits has been developed and applied to random access scan circuits of several hundred LSIs in mainframe computers.The results show that VFSIM is one or two orders of magnitude faster than a conventional fault simulator designed for random access scan circuits.A vectorized pattern parallel event-driven method is introduced for accelerating the fault simulator for synchronous sequential circuits.Utilizing the concept of unobservable regions (UOR), in which simulation of temporarily unobservable faults is avoided, contributes greatly to further acceleration, especially for random access scan circuits.

The paper describes one of the methods to evaluate the design verification progress of logic simulation. In the development of the very large scale general purpose computer HITACHI M-680H/682H, the function test programs designed for the products have been directly used to verify the design in simulation. Test programs establish the definite goal and enable to extensively verify the design. The simulation techniques, which carry out at high speed the very large design described in different levels of abstraction, have developed for this purpose. The method has detected 30% of design errors of M-68X and effectively reduced its development time.

This paper describes new simulation which reduce the computing requirement of a gate level logic simulator. The logic circuit to be simulated is transformed into the smaller one. The number of events as well as the storage necessary for expressing the logic circuits are decreased. Also, the evaluation of gates becomes faster by predicting whether a gate's input signal change would cause the gate's output signal change or not. Our simulator with these techniques has dealt with the logic of some 1,200,000 gates and has saved the computer processing time in developing our computer products.