Abstract { This paper describes the use of Uni ed System Construction tools under development at the University of Southern California. The goal of the project is to automate the construction of heterogeneous, applicationspeci c systems. Key elements of the USC system include multiprocessor synthesis, multi-chip datapath synthesis, memory-intensive synthesis, and multi-chip partitioning. The tools were applied to design of an image compression chip set, and results of using these tools are reported on here. Our results are comparable to manual designs reported in the literature. 1

This paper describes two experiments designed to show the effects of wiring area and delay and unused area on final chip characteristics.An example behavioral specification is used to produce a range of automatically synthesized designs with varying constraints on cost and performance, using both pipelined and nonpipelined design styles.An analysis of chip layouts is performed, and recommendations for future high-level synthesis programs are given.