In this paper an asynchronous TSC two-rail code error indicator is presented. Such an error indicator memorises error indications {00,11} generated by TSC checkers with time duration greater than a tolerant limit T and can be used to detect not only faults that cause logical errors bat also faults that cause additional delays. Thus, concurrent detection, of delay faults inside the checkers is an additional application of the proposed circuit. The proposed TSC error indicator is more efficient than the TSC error indicator presented by Gaitanis (see IEEE Trans. Comput., vol. 34, no. 8, p. 753-61, 1985) which, to the authors' knowledge, is the only existing TSC error indicator in the open literature.

A Totally Self Checking (TSC) reconfigurable duplication system with respect to single cell fault model is described in this paper. It consists of two identical functional self checking units that receive the same inputs. TSC checkers are associated with each functional unit and produce either a normal indication when the output is correct or an error indication when the output is incorrect. The circuit that receives the indications of the two TSC checkers is a TSC decision circuit that produces two indication outputs E and F, respectively. E indicates mainly the status of the outputs of units while F indicates the existence of internal faults in the TSC decision circuit. Such indications can be used for the non stop repair before redundancy is exhausted. Thus continuous operation is preserved increasing the availability and the reliability of the system.

The design of a novel class of totally self-checking (TSC) checkers with two separate output indications E/sub N/ and F/sub N/ is described. F/sub N/ is independent of input errors and indicates internal faults only. On the other hand, the output E/sub N/ indicates input errors as well as a small number of internal faults. This design technique, while improving the maintainability of the TSC networks that locate the fault in the functional circuit or in the checker itself, also increases the correct response probability of the error indication output E/sub N/. The TSC checkers presented utilize redundant copies of a given normal TSC checker which are monitored by a TSC reduction circuit operating like a TSC vote taker. The TSC reduction circuits can be easily designed using an algebraic approach based on a two-element Boolean algebra with a more efficient set of self-checking operator blocks.>

A totally self-checking triple modular redundancy (TSC-TMR) system consists of a conventional TMR system monitored by a TSC circuit with two outputs indicating information errors and internal faults. The internal fault indication is independent of the output information errors and indicates masked errors of modular units or faults in the monitoring circuit itself. The information error indication depends mainly on the output information errors and it can be used as a stop signal preventing the propagation of erroneous outputs. This scheme of fault-tolerant systems is very simple and reliable compared to the known TMR systems with self-checking capabilities and achieves a high degree of availability and maintainability. The TSC error checking circuit has been designed by applying a new algebraic technique with two basic operator blocks performing the AND and XOR operations on error indication variables.>

A design technique for totally self-checking (TSC) error correcting/detection (C/D) circuits of single error correcting, double error detection (SEC/DED) codes is described. The structure of these circuits achieves concurrent fault detection and location under normal input conditions. A separate internal fault indication is provided. This improves the reliability, maintainability, and availability of the entire fault-tolerant system because faults are repaired before the appearance of input errors. The error C/D circuits are composed of TSC error detectors, error locators, and error correctors. These circuits are two-rail TSC checkers and are designed using an algebraic approach.>

In this paper we give methods for the construction of systematic t-random error correcting and all unidirectional error detecting codes. Also we give the encoding/decoding algorithms and discuss their implementation.

This paper presents totally self-checking (TSC) checkers for low-cost AN codes with generator A = 2r −1. These checkers are composed of two different parts. The first part is a TSC residue generator modulo (22r − 1), and the second part is a TSC checker for the same low-cost AN code with code length 2r. There are r output lines with two code output states: the all O's and the all 1's states, which can be reduced to 1-out-of-2 code output states by using a "counter-driven comparator." These checkers have the same number of output lines, but they are faster, more economical, and more reliable, compared to the corresponding checkers based on the computation of the residue modulo 2r − 1 of the input states.

This correspondence presents a totally self-checking error indicator for solving the practical problem of monitoring the TSC checkers. We consider TSC checkers designed for checking coded information (data or address) or periodic signals with tolerable transient failures smaller than a constant time limit T, which depends on the propagation delay of the used logic elements. This circuit provides normal indication outputs (01) or (10) and error indication outputs (11) or (00). Permanent failures or transient failures with time duration greater than T result in a permanent error indication, which remains until reset. Provided that an assumed fault occurs within the checker, the permanent error indication output is produced at most after four input changes from (01) to (10) or from (10) to (01).

The paper presents a new method for designing efficient TSC checkers for m-out-of n codes. The method is based on the partitioning of the input code variables into an arbitrary number of r classes. The paper establishes the necessary design conditions that must hold among m, n and r. The checker is basically composed of an m/n to l/z subchecker concatenated with an l/z to 1/2 subchecker. A cost analysis performed reveals that the most economical checkers are obtained for values of r equal to 3, or 4 for the majority of m/n codes with n ≤ 4m. Comparison with earlier designs reveals impressive improvement both in logic complexity and testing complexity.

This paper considers AN arithmetic codes with radix r > 2 and binary-coded digits (BCr) using weights. The error-correcting capability of the AN codes is single bit within any BCr digit, that is, the corrected errors are of the form ± wirj where wi are the weights of the BCr code. The paper characterizes a class of AN codes having a generator of the form A = r · p where r|r − 1 or τ|r + 1 and p prime is greater than r − 1 or r + 1. It is shown that these codes, under certain conditions, are near perfect.

This paper presents a new class of AN codes of high efficiency capable of correcting single errors in radix-r arithmetic with the binary coded digits—BCr—system. The errors corrected within a single radix-r digit are single errors of the binary digits with weight ±wi≤ r–1,i=1,2,···, m, which are used to encode the BCr digits. The corresponding arithmetic unit is made out of slices, one for each BCr digit. The AN codes considered have a generator A of the form A = τ·p where τ, p odd and rp=n-1 ≤ τk± 1. The criteria are applied to the BCD system, and we determine all τ < 100 and p < 200 for the most important BCD codes with weights ± wi < r –1, i = 1, 2, 3, 4. For each BCD code, the paper gives the numbers τ < 100 for which AN codes exist, and the maximum code efficiency E = 2·m·k/(A-1) attained at some p < 200.

This note is concerned with the design of fast totally self-checking checkers for m-out-of-(2m ± 1) codes. The new method uses only three levels of gates, and is based on the partitioning of the input lines into m blocks of two lines per block except for the last block. A first level of two-input AND and OR gates realizes the majority functions T(ki ≥ 1) and T(ki ≥ 2). These are combined through AND gates of a second level into the so-called product functions Pj1j2...jm, one for each class of input codewords that have jl, j2,···, jm 1's in the corresponding blocks of the input lines. Finally, two OR gates (third level) partition the product functions into two. The property of totally self-checking operation is achieved through the proper partitioning of the product functions into two classes. This note presents a systematic method of such partitioning. Also, the note determines the cost of these checkers and compares them to previous designs.

The correspondence deals with the fail-safe realization of synchronous sequential machines under the assumption that the next-state functions are in any positive form. This leads to new classes of assignments called positive fail-safe assignment's (PFSA) The feasibility conditions of such assignments are given and systematic procedures are presented for deriving them using k-out-of-n codes.

A new type of double-rank sequential circuit is presented in this paper. This new type, called Type 4, differs from its predecessor types in that it employs a Boolean memory as rank-1 memory instead of flip-flops. The Boolean memory used is an aggregate of symmetric Boolean memories with 1-out-of-n state encodings. A procedure for realizing a sequential machine by a Type 4 double-rank sequential circuit is also presented in the paper.

A new approach is presented for the minimization of the word length of the control store in microprogrammed computers. Given the set of microinstructions and the set of microcommands of a microprogrammed computer a minimal subset of microcommands are determined so that every other microcommand not contained in this minimal subset to be generated from it by a single AND or OR gate. The problem of finding such minimal subsets of microcommands is formulated as a Boolean function simplification problem and is based upon an extension of the notion of the minimal dependence sets of a Boolean function.

A new method is presented for determining all minimal dependence sets, irredundant normal forms, and irredundant normal forms of minimal dependence sets of a Boolean function f. The method reduces the above problems into those of determining all minimal positive dependence sets, irredundant positive normal forms, and irredundant positive normal forms of minimal positive dependence sets, respectively, of a Boolean function f* corresponding to f. For each problem a corresponding cover formula is developed such that the prime implicants of it are in one-to-one correspondence to all possible solutions.

This correspondence presents a new unified approach for defining and finding the various types of partition pairs ("d", "t","r","j") of a sequential machine. The notion of separation (distinguishability) of states is the key factor of the new approach. By this and the notion of transition sets one can easily find all maximal partitions τ which are in "d","t","r", and "j" relation with a given partition ρ.