The field of human motion prediction has gained prominence, finding applications in various domains such as intelligent surveillance and human–robot interaction. However, predicting full-body human motion poses challenges in capturing joint interactions, handling diverse movement patterns, managing occlusions, and ensuring real-time performance. To address these challenges, the proposed model adopts a skeleton-parted strategy to dissect the skeleton structure, enhancing coordination and fusion between body parts. This novel method combines transformer-enabled graph convolutional networks for predicting human motion in 3-D skeleton data. It integrates a temporal transformer (T-Transformer) for comprehensive temporal feature extraction and a spatial graph convolutional network (S-GCN) for capturing spatial characteristics of human motion. The model's performance is evaluated on two comprehensive human motion datasets, Human3.6M and CMU motion capture (CMU Mocap), containing numerous videos encompassing short and long human motion sequences. Results indicate that the proposed model outperforms state-of-the-art methods on both datasets, significantly improving the average mean per joint positional error (avg-MPJPE) by 3.50% and 11.45% for short-term and long-term motion prediction, respectively. Similarly, on the CMU Mocap dataset, it achieves avg-MPJPE improvements of 2.69% and 1.05% for short-term and long-term motion prediction, respectively, demonstrating its superior accuracy in predicting human motion over extended periods. The study also investigates the impact of different numbers of T-Transformers and S-GCNs and explores the specific roles and contributions of the T-Transformer, S-GCN, and cross-part components.

It is a nontrivial task to manage crowds in public places and recognize unacceptable behavior (such as violating social distancing norms during the COVID-19 pandemic). In such situations, people should avoid loitering (unnecessary moving out in public places without apparent purpose) and maintain a sufficient physical distance. In this study, a multi-object tracking algorithm has been introduced to improve short-term object occlusion, detection errors, and identity switches. The objects are tracked through bounding box detection and with linear velocity estimation of the object using the Kalman filter frame by frame. The predicted tracks are kept alive for some time, handling the missing detections and short-term object occlusion. ID switches (mainly due to crossing trajectories) are managed by explicitly considering the motion direction of the objects in real time. Furthermore, a novel approach to detect unusual behavior of loitering with a severity level is proposed based on the tracking information. An adaptive algorithm is also proposed to detect physical distance violation based on the object dimensions for the entire length of the track. At last, a mathematical approach to calculate actual physical distance is proposed by using the height of a human as a reference object which adheres more specific distancing norms. The proposed approach is evaluated in traffic and pedestrian movement scenarios. The experimental results demonstrate a significant improvement in the results.

Abstract Recognizing entities and their corresponding roles are important in human activity recognition. In light of recent advancements, the primary emphasis is recognizing the abstract activities involving person‐person interaction. The contribution of this work is proposing an architecture, which utilizes the knowledge of the human body parts coordinates in role detection of each individual. The network preprocesses the coordinates to build intra‐body and inter‐body features. The extracted features build the relationship between the interacting bodies and learn the temporal relation corresponding to each role using the human memory‐inspired hierarchical temporal memory. The model is tested on vague samples of mutual actions in the experimental work. The model is found robust in action and role recognition tasks and performed well per expectations.

In the past few years, some fusion-based approaches have been proposed to constitute discriminatory features for iris liveness detection. However, several methods exist in the literature for iris feature extraction and, thus, identifying an optimal composite of such features is still a vital challenge. This article also proposes a score-level fusion of two distinct domain-specific features, i.e., multiple binarized statistical image feature (BSIF) and DenseNet-based features. However, instead of randomly scrutinizing such features, statistical tests are executed on six predominant iris features to identify the optimal feature set to combine. Particularly, this work emphasizes textured-lens-based presentation attacks and aims to identify the type of contact lenses within the iris samples. The experimental analysis depicts that the domain-specific features substantially outperform the generic features while discriminating live iris from the artifacts. Furthermore, the proposed fusion-based approach is assessed on three iris datasets and the outcomes are compared with various state of the arts using three validation protocols in terms of equal error rate (EER). The comparative analysis perceived that the proposed method obtains a significant performance gain over the existing approaches and offers an improved benchmark for both, iris liveness detection and contact lens identification.

Improving the network lifetime is a major concern in Wireless Sensor Networks (WSNs) due to the limited network resources. As the sensor nodes are usually deployed in a random fashion across the network area, network-wide energy optimization becomes a challenge. An energy-optimized WSN offers improved fault tolerance, and this can be further enhanced with the help of Software Defined Networking (SDN). Hence, a Software Defined WSN (SDWSN) based energy efficient approach is proposed in this paper to improve the performance of the network. The proposed approach discusses an Energy Optimized Multi-Constrained Sustainable Routing (EOMCSR) model. This model formulates a Mixed Integer Linear Programming (MILP) problem to optimize the network resource based energy consumption in SDWSN. The simulation results are compared with the existing SDWSN and traditional WSN approaches with respect to the performance metrics for different numbers of rounds. The experimental results verify that EOMCSR achieves an efficiency of around8%and48%for average energy per node in comparison to the SDWSN approach (MES) and traditional approach (E-TORA) respectively, after100rounds for200nodes. Similarly, an efficiency of around36%and60%is achieved for the number of dead nodes. In addition to this, the proposed approach is also tested under different network scenarios w.r.t. multiple network performance metrics, and substantial improvements have been obtained w.r.t. each performance metric.

Visual object tracking is an important function in many real-time video surveillance applications, such as localization and spatio-temporal recognition of persons. In realworld applications, an object detector and tracker must interact on a periodic basis to discover new objects, and thereby to initiate tracks. Periodic interactions with the detector can also allow the tracker to validate and/or update its object template with new bounding boxes. However, bounding boxes provided by a state-of-the-art detector are noisy, due to changes in appearance, background and occlusion, which can cause the tracker to drift. Moreover, CNN-based detectors can provide a high level of accuracy at the expense of computational complexity, so interactions should be minimized for real-time applications. In this paper, a new approach is proposed to manage detector-tracker interactions for trackers from the Siamese-FC family. By integrating a change detection mechanism into a deep Siamese-FC tracker, its template can be adapted in response to changes in a target's appearance that lead to drifts during tracking. An abrupt change detection triggers an update of tracker template using the bounding box produced by the detector, while in the case of a gradual change, the detector is used to update an evolving set of templates for robust matching. Experiments were performed using state-of-the-art Siamese-FC trackers and the YOLOv3 detector on a subset of videos from the OTB-100 dataset that mimic video surveillance scenarios. Results highlight the importance for reliable VOT of using accurate detectors. They also indicate that our adaptive Siamese trackers are robust to noisy object detections, and can significantly improve the performance of Siamese-FC tracking.

One of the major challenges in wireless sensor network (WSN) research is to curb down congestion in the network's traffic, without compromising with the energy of the sensor nodes. In this work, we address the problem of congestion in the nodes of a WSN using Learning Automata (LA)-based adaptive learning approach. Our primary objective, using this approach, is to adaptively make the processing rate (data packet arrival rate) in the nodes equal to the transmitting rate (packet service rate), so that the occurrence of congestion in the nodes is seamlessly avoided. We maintain that the proposed algorithm, named as Learning Automata-Based Congestion Avoidance Algorithm in Sensor Networks (LACAS), can counter the congestion problem in WSNs effectively. The results obtained through the experiments with respect to important performance criteria showed that the proposed algorithm is capable of successfully avoiding congestion in typical WSNs requiring a reliable congestion control mechanism.

One of the major challenges in wireless sensor network (WSN) research is to curb down congestion in the network's traffic, without compromising with the energy of the sensor nodes. Congestion affects the continuous flow of data, loss of information, delay in the arrival of data to the destination and unwanted consumption of significant amount of the very limited amount of energy in the nodes. Obviously, in healthcare WSN applications, particularly in the ones that cater to medical emergencies or in the ones that closely monitor critically ailing patients, it is desirable in the first place to avoid congestion from occurring and even if it occurs, to reduce the loss of data due to congestion. In this work, we address the problem of congestion in the nodes of healthcare WSN using a learning automata (LA)-based approach. Our primary objective in using this approach is to adaptively make the processing rate (data packet arrival rate) in the nodes equal to the transmitting rate (packet service rate), so that the occurrence of congestion in the nodes is seamlessly avoided. We maintain that the proposed algorithm, named as learning automata-based congestion avoidance algorithm in sensor networks (LACAS), can counter the congestion problem in healthcare WSNs effectively. An important feature of LACAS is that it intelligently' learns' from the past and improves its performance significantly as time progresses. Our proposed LA based model was evaluated using simulations representing healthcare WSNs. The results obtained through the experiments with respect to performance criteria having important implications in the healthcare domain, for example, the number of collisions, the energy consumption at the nodes, the network throughput, the number of unicast packets delivered, the number of packets delivered to each node, the signals received and forwarded to the medium access control (MAC) layer, and the change in energy consumption with variation in transmission range, have shown that the proposed algorithm is capable of successfully avoiding congestion in typical healthcare WSNs requiring a reliable congestion control mechanism.

As the power consumption of modern high-performance microprocessors increases beyond 100 W, power becomes an increasingly important design consideration. This paper presents a novel technique to simulate power supply voltage variation as a result of varying activity levels within the microprocessor when executing typical software. The voltage simulation capability may be added to existing microarchitecture simulators that determine the activities of each functional block on a clock-by-clock basis. We then discuss how the same technique can be implemented in logic on the microprocessor die to enable real-time computation of current consumption and power supply voltage. When used in a feedback loop, this logic makes it possible to control the microprocessor's activities to reduce demands on the power delivery system. With on-die voltage computation and di/dt control, we show that a significant reduction in power supply voltage variation may be achieved with little performance loss or average power increase.

Datapath design is one of the most critical elements in the design of a high performance microprocessor. However datapath design is typically does manually, and is often custom style. This adversely impacts the overall productivity of the design team, as well as the quality of the design. In spite of this, very little automation has been available to the designers of high performance datapaths. In this paper we present a new “macro-driven” approach to the design of datapath circuits. Our approach, referred to as SMART (Smart Macro Design Advisor), is based on automatic generation of regular datapath components such as muxes, comparators, adders etc., which we refer to as datapath macros. The generated solution is based on designer provided constraints such as delay, load and slope, and is optimized for a designer provided cost metric such as power, area. Results on datapath circuits of a high-performance microprocessor show that this approach is very effective for both designer productivity as well as design quality.

Current microprocessor architectures become more and more dominated by the data access bottlenecks in the cache, system bus and main memory subsystems. These also have a major influence on the system (board-level) power consumption. In practice this means lower energy consumption for a given throughput requirement. In the booming domain of (largely embedded) cost-sensitive communication and multi-media applications, more and more implementations make use of microprocessor based platforms for flexibility reasons. However, in order to provide sufficiently high data throughput at reasonable power consumption for these demanding applications, novel solutions for the memory access and data transfer will have to be introduced. These will have to be situated both at the processor architecture and the algorithm/compiler level. The question we want to address in this paper is what would these solutions look like. We show that they will be based on processor architecture optimizations, on novel approaches in the application of compiler technology, and on exploiting the interface between the system hardware and software.

Power dissipation and thermal issues are increasingly significant in modern processors. As a result, it is crucial that power/performance tradeoffs be made more visible to chip architects and even compiler writers, in addition to circuit designers. Most existing power analysis tools achieve high accuracy by calculating power estimates for designs only after layout or floorplanning are complete. In addition to being available only late in the design process, such tools are often quite slow, which compounds the difficulty of running them for a large space of design possibilities. This paper presents Wattch, a framework for analyzing and optimizing microprocessor power dissipation at the architecture-level. Wattch is 1000X or more faster than existing layout-level power tools, and yet maintains accuracy within 10% of their estimates as verified using industry tools on leading-edge designs. This paper presents several validations of Wattch's accuracy. In addition, we present three examples that demonstrate how architects or compiler writers might use Wattch to evaluate power consumption in their design process. We see Wattch as a complement to existing lower-level tools; it allows architects to explore and cull the design space early on, using faster, higher-level tools. It also opens up the field of power-efficient computing to a wider range of researchers by providing a power evaluation methodology within the portable and familiar SimpleScalar framework.

No abstract available.

Article An architectural solution for the inductive noise problem due to clock-gating Share on Authors: Mondira Deb Pant Georgia Institute of Technology, Atlanta, GA Georgia Institute of Technology, Atlanta, GAView Profile , Pankaj Pant View Profile , D. Scott Wills Georgia Institute of Technology, Atlanta, GA Georgia Institute of Technology, Atlanta, GAView Profile , Vivek Tiwari Intel Corporation, Santa Clara, CA Intel Corporation, Santa Clara, CAView Profile Authors Info & Claims ISLPED '99: Proceedings of the 1999 international symposium on Low power electronics and designAugust 1999 Pages 255–257https://doi.org/10.1145/313817.313938Online:17 August 1999Publication History 42citation309DownloadsMetricsTotal Citations42Total Downloads309Last 12 Months0Last 6 weeks0 Get Citation AlertsNew Citation Alert added!This alert has been successfully added and will be sent to:You will be notified whenever a record that you have chosen has been cited.To manage your alert preferences, click on the button below.Manage my AlertsNew Citation Alert!Please log in to your account Save to BinderSave to BinderCreate a New BinderNameCancelCreateExport CitationPublisher SiteGet Access

Power consumption has become one of the biggest challenges in high-performance microprocessor design. The rapid increase in the complexity and speed of each new CPU generation is outstripping the benefits of voltage reduction and feature size scaling. Designers are thus continuously challenged to come up with innovative ways to reduce power, while trying to meet all the other constraints imposed on the design. This paper presents an overview of the issues related to power consumption in the context of Intel CPUs. The main trends that are driving the increased focus on design for low power are described. System and benchmarking issues, and sources of power consumption in a high-performance CPU are briefly described. Techniques that have been tried on real designs in the past are described. The role of CAD tools and their limitations in this domain will also be discussed. In addition, areas that need increased research focus in the future are also pointed out.

The need to reduce the power consumption of the next generation of digital systems is clearly recognized at all levels of system design. At the system level, power management is a very powerful technique and delivers large and unambiguous savings. The ideas behind power management can be extended to the logic level. This would involve determining which parts of a circuit are computing results that will be used and which are not. The parts that are not needed are then "shut off". This paper describes an approach termed guarded evaluation, which is an implementation of this idea. A theoretical framework and the algorithms that form the basis of the approach are presented. The underlying idea is to automatically determine the parts of the circuit that can be disabled on a per-clock-cycle basis. This saves the power used in all the useless transitions in those parts of the circuit. Initial experiments indicate substantial power savings and the strong potential of this approach for a large number of benchmark circuits. While this paper presents the development of these ideas at the logic level of design, the same ideas have direct application at the register-transfer level of design also.

Power is becoming a critical constraint for designing embedded applications. Current power analysis techniques based on circuit-level or architectural-level simulation are either impractical or inaccurate to estimate the power cost for a given piece of application software. In this paper, an instruction-level power analysis model is developed for an embedded digital signal processor (DSP) based on physical current measurements. Significant points of difference have been observed between the software power model for this custom DSP processor and the power models that have been developed earlier for some general purpose commercial microprocessors. In particular, the effect of circuit state on the power cost of an instruction stream is more marked in the case of this DSP processor. In addition, the processor has special architectural features that allow dual memory accesses and packing of instructions into pairs. The energy reduction possible through the use of these features is studied. The on-chip Booth multiplier on the processor is a major source of energy consumption for DSP programs. A microarchitectural power model for the multiplier is developed and analyzed for further power minimization. In order to exploit all of the above effects, a scheduling technique based on the new instruction-level power model is proposed. Several example programs are provided to illustrate the effectiveness of this approach. Energy reductions varying from 26% to 73% have been observed. These energy savings are real and have been verified through physical measurement. It should be noted that the energy reduction essentially comes for free. It is obtained through software modification, and thus, entails no hardware overhead. In addition, there is no loss of performance since the running times of the modified programs either improve or remain unchanged.

No abstract available.

Embedded computer systems are characterized by the presence of a dedicated processor and the software that runs on it. Power constraints are increasingly becoming the critical component of the design specification of these systems. At present, however, power analysis tools can only be applied at the lower levels of the design-the circuit or gate level. It is either impractical or impossible to use the lower level tools to estimate the power cost of the software component of the system. This paper describes the first systematic attempt to model this power cost. A power analysis technique is developed that has been applied to two commercial microprocessors-Intel 486DX2 and Fujitsu SPARClite 934. This technique can be employed to evaluate the power cost of embedded software. This can help in verifying if a design meets its specified power constraints. Further, it can also be used to search the design space in software power optimization. Examples with power reduction of up to 40%, obtained by rewriting code using the information provided by the instruction level power model, illustrate the potential of this idea.>

The last couple of years have seen the addition of a new dimension in the evaluation of circuit quality -its power requirements.Low power circuits are emerging as an important application domain, and synthesis for low power is demanding attention.The research presented in this paper addresses one aspect of low power synthesis.It focuses on the problem of mapping a technology independent circuit to a technology specific one, using gates from a given library, with power as the optimization metric.Several issues in modeling and measuring circuit power, as well as algorithms for technology mapping for low power are presented here.Empirically, it is observed that a significant variation in the power consumption is possible Just by varying the choice of gates.Technology mapping for low power provides circuits with up to 24% lower power requirements than those obtained by technology mapping for area.

Superscalar implementations of RISC architectures are emerging as the dominant high-performance microprocessor technology for the mid-1990's. This paper proposes and evaluates a split data cache memory design, a new memory system ehancement for superscalar processor architectures. This design allows floating-point and integer memory access to be executed in parallel. The configuration is well matched to the dual-path execution hardware of many current superscalar processors. It doubles peak bandwidth without the expense or complexity of multi-ported memory, and increases the processor's ability to exploit fine-grained parallelism. The reported simulation results show that by using this enhancement, a speedup of more than 1.5 over the traditional unified cache model can be achieved on some standard benchmarks. The speedup is not uniform among all programs. Several hypotheses are presented and experimentally validated to explain these results.>