This paper explores the characteristics of Monotonic-Static CMOS and its potential applications in gate leakage reduction in a hypothetical 22nm Bulk-Si technology with significant gate leakage currents. Using test circuits consisting of NAND and NOR logic gates, we performed a comparison among static, monotonic static and domino logic in terms of various properties including power, delay, noise margin and area. Comparisons were done over a wide range of possible transistor widths to fully characterize the tradeoffs for each circuit type. Experimental results show that MS-CMOS has potential advantages in terms of stand-by power, evaluation speed and noise margin in such a technology.

This paper reviews the use of monotonic static CMOS logic gates in scaled technologies where gate leakage currents become significant. High-level tradeoffs are discussed, and some experiments are constructed to evaluate the gate-level performance tradeoffs in a hypothetical standard 65nm CMOS technology. At the gate level, significant improvements in static power consumption are possible without reduction in evaluation delays, but the tradeoffs vary as the conditions and the amount of skewing are changed. Noise tolerance is shown to fall as skewing is increased. The tradeoffs are studied both at the gate level and in a mixed static/monotonic static CMOS design.

This paper reviews the use of skewed monotonic static CMOS logic gates in scaled technologies where gate leakage currents become significant. High-level tradeoffs and synthesis approaches are discussed, and some experiments are constructed to evaluate the gate-level performance tradeoffs in a hypothetical standard 65nm CMOS technology. At the gate level, significant improvements in static power consumption are possible without reduction in evaluation delays, but the tradeoffs vary as the conditions and the amount of skewing are changed. NAND forms are still preferred as the gate leakage grows.

In this paper, we first study the behavior of gate leakage current in a simple inverter. We make some important observations about the gate leakage in both PMOS and NMOS devices. We then study the trade off between power and delay in a standard inverter within a particular buffer chain when reducing the size of the pull-down device. In the last part of this paper, we present an alternate leakage suppressed inverter for driving large loads. We finally compare the performance of our proposed circuit with those of standard and scaled-down inverters and show that we can significantly reduce the standby power in certain situations with a modest reduction in speed.

Channel subthreshold and gate leakage currents are predicted by many to become much more significant in advanced CMOS technologies and are expected to have a substantial impact on logic circuit design strategies. To reduce static power, techniques such as the use of monotonic logic and management of various evaluation and idle modes within logic stages may become important options in circuit optimization. In this paper, we present a general, multilevel model for logic blocks consisting of logic gates that include a wide range of options for static power reduction, in both the domains of topology and timing. Existing circuit techniques are classified within this framework and experiments are presented showing how aspects of performance might vary across this range in a hypothetical technology. The framework also allows exploration of optimal mixing of techniques.

We present a unique FPGA that uses a mix of digital and large-signal analog computation for the simulation of gene regulatory networks. The prototype IC consists of a 4x5 array of configurable logic blocks along with programmable interconnect. It can simulate a network of pathways involving up to 20 genes and their associated proteins. The circuit design takes advantage of a number of analogies between CMOS circuits and gene networks. For example, a capacitor charge is used to represent a protein concentration, currents represent protein production, and a transistor switch network is used to compute the influences of activator and repressor proteins on gene expression. A simulation shows how the chip can predict oscillatory behavior in a particular well-known three-gene system.

Accuracy Management (AM) offers delay-oriented control of simulation accuracy in automated mixed-mode simulation of digital VLSI circuits. AM heuristics, with little additional computation, can achieve a required level of accuracy in output timing predictions while insuring computational efficiency by using simulations with appropriate levels of accuracy throughout a circuit. These results are demonstrated through both mathematical predictions on some benchmark circuit topologies, and actual mixed-mode timing simulations on large combinational circuit benchmarks. Simulation speedups of 5-10 over corresponding standard, wave-form relaxation-based circuit simulations are demonstrated.

The potential for saving energy by employing dynamic power supply scaling in an ATM (Asynchronous Transfer Mode) interface circuit is analyzed and simulated. Feedback is used to adjust the power supply based on how full the input buffer is. Either a DC-DC converter or multiple supply voltages can be used. Self-timed processing circuitry allows the feedback to control the speed fairly precisely, even incorporating variations in process and operating conditions into the loop. The trade-offs and requirements for buffer size, converter response time, and control algorithm are discussed. Significant energy savings are possible if the power supply voltage can be adjusted quickly. A similar analysis can be used for applications other than an ATM interface.

In this paper, we revisit three of the well known optimization results in CMOS transistor sizing with the energy-delay product as a new metric. We study the absolute sizes of and the ratio between n-channel and p-channel transistor widths in uniform logic, the optimal distance between repeaters in an RC line, and the optimum number of inverter stages, along with their sizes, needed to drive a large load capacitance. Results, both theoretical and numerical, show that in general the optimum solutions for energy-delay lead to smaller designs than the ones obtained for minimum delay.

We explore what is needed to improve and automate the process of designing a broadband ATM switch, i.e., determining the "optimal" switch parameters given hardware costs and constraints on quality of service. We present a cost model for implementation with CMOS integrated circuits, based on some prototype designs that include both input and output buffering, and combine this with a simple method for rough performance analysis to allow quick design evaluation. Experiments are presented for a range of specifications, based on an automated exhaustive search algorithm and a framework for using nonlinear integer optimization to improve efficiency in the future is developed.

In this paper the non-linear and complex relationship between packet loss probability and average packet delay for an input/output buffered ATM switch is studied thoroughly using our previously published analysis model. The main contribution is insight into the behavior of the switch and better understanding of the buffer size trade-offs under various traffic conditions speed-up factors, and buffer sizes. For different traffic conditions and buffer sizes, several distinct regions are identified and the behavior of the switch in those regions is explained. The results presented here can provide the basis for an optimum VLSI design methodology for input/output-buffered switches.

Quality of service and network controllability are issues that have yet to be clearly defined for broadband packet switching networks. One method of influencing the quality of service and the controllability of packet switched networks is queue scheduling. Unfortunately, defining an optimal queue scheduling method is highly dependent upon the cost function chosen for a particular switch implementation. Therefore, the authors propose a VLSI generic queue scheduler that can emulate a wide variety of queue scheduling methods. They implement the VLSI generic queue scheduler using a VLSI system synthesis tool, OASIS, and through measurements explore the size and speed of various system configurations. The process of employing some scheduling methods in this architecture is also detailed.>

Timing jitter is an important factor in limiting throughput in high-performance digital circuits, e.g. those using techniques such as wave pipelining. Many of the sources of timing jitter, such as physical noise, coupling noise, and delta-I noise, are best modeled with random shifts in signal voltages. A new analysis technique for translating such noise into timing jitter characteristics is presented. The circuit is linearized about its nominal behavior and the resulting time-varying system is discretized so that the mapping from voltage noise to timing jitter can be easily calculated and characterized. In addition, the use of differential circuit techniques to improve noise immunity is discussed.>

A circuit architecture that can produce a high-frequency digital test pattern by merging a number of low-frequency patterns is implemented. This merging is accomplished using only delay elements and combinational logic, so the circuit's speed is not limited by clock constraints. Two prototype circuits using transistor-transistor logic (TTL) and emitter-coupled logic (ECL) are presented to demonstrate the approach and to explore implementation issues.>

The use of VLSI technology to speed up cyclic redundancy checking (CRC) circuits used for error detection in telecommunications systems is investigated. By generalizing the analysis of a parallel prototype, performance is estimated over a wide range of external constraints and design choices. It is shown that parallel architectures fall somewhat short of ideal speedups in practice, but they should still enable current CMOS technologies to go well beyond 1 Gb/s data rates.>

Routing tables for communication networks can be designed using many different approaches, including table lookup, content-addressable memory (CAM), hashing, and tries. The authors compare these approaches in the context of custom VLSI implementation. For tables with a small number of entries and a large address space, CAMs can be very cost effective. If only RAM is available, it is shown that tries, of which simple table lookup is a special case, provide a useful architecture. Also considered is a new variation, table partitioning, which constitutes a useful compromise between the conventional CAM and a trie.>

An analysis tool is introduced that measures subcircuit coupling and error attenuation in waveform relaxation (WR) circuit simulation algorithms with full dimensionality. Unlike current methods that use heuristics to calculate scalar gains, this method capture all the effects of error attenuation over time and space. An example is provided of how this technique can be used to study the performance of various partitions, schedules, and WR algorithms on a wide range of technologies, including BiCMOS.>

It is shown how careful parameter reduction can be used to produce simple but very accurate macromodels for complex logic circuits. To model input and output voltage waveforms, the authors use approximations that are time-scaled and time-shifted versions of 'typical' waveforms rather than highly simplified waveforms such as ramps. To model devices, they use scaled nonlinear characteristics. Furthermore, it is shown that the technique of scaling and shifting time to obtain the response of a large class of circuits from that of a single test case applies to very complex circuit models, and can be used to handle two input parameters in a very simplified manner. Finally, to illustrate the reduced-parameter macromodeling process, the authors test a simple table-lookup CMOS delay estimation algorithm.>

Standard time-division multiplexer circuits use variations on a finite-state-machine approach to sequence through all input data. The authors present an alternate multiplexer architecture that avoids both the bottleneck of waiting for latches to settle and the problems of distributing a high-frequency clock signal. The authors have investigated the tradeoffs between various architectures by fabricating and testing a CMOS implementation of both a matched-delay and shift-register-based architecture. Experiments show that the proposed approach can be competitive, but additional experiments are needed to further understand its practical limits.>

Fundamental limits on the communication capabilities of massively parallel multiprocessors are investigated. It is shown that in the limit of machines of infinite extent in which the number of processors per unit volume is constant and in which the communication bandwidth from each processor to its neighbors depends only on their separation distance, interprocessor communication must fall off faster than the fourth power of distance. For machines of finite size, communication energy density is used as a metric to compare various machine sizes and packaging densities. For instance, for machines with spherical symmetry and uniform communication requirements, the peak density depends on the number of processors to the 4/3 power and the number of processors per unit volume to the 2/3 power.>

A new algorithm that produces a sequence of closed-form upper and lower bounds on the response of a very general class of linear RC networks is presented in this paper. The bounds approach arbitrarily close to the actual response by using a successive relaxation method. Since the accuracy of the final bounds can be improved through additional computation, the algorithm is more flexible than previous bounding algorithms. Furthermore, the class of networks considered is more general. The new bounding algorithm treats leaky, linear RC mesh networks in which all capacitors and voltage sources are grounded. Such networks are often used to model large digital MOS circuits in timing analysis programs. The general theory behind the algorithm is presented along with some experimental results.

This correspondence examines integrated-circuit logarithmic arithmetic units which include adders, subtracters, multipliers, and dividers. The design of these arithmetic units is reviewed, and an example arithmetic unit which performs multiplication followed by addition is designed in detail. The design results are used to develop a size and speed comparison of integrated-circuit logarithmic and fixed-point arithmetic units. This comparison is exercised through a video signal processing example. It is concluded from this comparison that logarithmic arithmetic units are smaller than, and as fast as, fixed-point arithmetic units with comparable capabilities in digital signal processing applications characterized by large dynamic range and moderate computational accuracy requirements. Further, this comparison quantitatively illustrates the interaction of digital-signal-processing and integrated-circuit issues in the design of special-purpose digital signal processors.