Soft error is a type of transient errors that occur due in part to reductions in capacitance and operating voltages in modern electronic components. Recently, the problem of soft errors has become more prevalent due to several design factors, including aggressive device scaling and newer energy-efficient designs, thus significantly threatening the reliability of computer systems. Since the occurrence of soft errors is non-deterministic, detecting them and recovering from them can be quite challenging. A common way to detect soft errors is to execute two identical program instances and then compare their results. Although this approach is effective, it is not efficient as both non-trivial computation and memory resources must be invested to support such redundant executions.

Non-volatile memory express (NVMe) based SSDs and the NUMA platform are widely adopted in servers to achieve faster storage speed and more powerful processing capability. As of now, very little research has been conducted to investigate the performance and energy efficiency of the state-of-the-art NUMA architecture integrated with NVMe SSDs, an emerging technology used to host parallel I/O threads. As this technology continues to be widely developed and adopted, we need to understand the runtime behaviors of such systems in order to design software runtime systems that deliver optimal performance while consuming only the necessary amount of energy. This paper characterizes the runtime behaviors of a Linux-based NUMA system employing multiple NVMe SSDs. Our comprehensive performance and energy-efficiency study using massive numbers of parallel I/O threads shows that the penalty due to CPU contention is much smaller than that due to remote access of NVMe SSDs. Based on this insight, we develop a dynamic "lesser evil" algorithm called ESN, to minimize the impact of these two types of penalties. ESN is an energy-efficient profiling-based I/O thread scheduler for managing I/O threads accessing NVMe SSDs on NUMA systems. Our empirical evaluation shows that ESN can achieve optimal I/O throughput and latency while consuming up to 50% less energy and using fewer CPUs.

Algorithmic methods are demonstrated for information extraction from table header elements, including data categories and data hierarchies. The table headers are found with the Minimum Index Point Search algorithm. The header-path alignment and header completion algorithms yield database-ready table content and configuration statistics on a random sample of 400 diverse tables with ground truth and 1120 tables without ground truth from international statistical data sites.

Recent studies have found that parallel garbage collection performs worse with more CPUs and more collector threads. As part of this work, we further investigate this enomenon and find that poor scalability is worst in highly scalable Java applications. Our investigation to find the causes clearly reveals that efficient multi-threading in an application can prolong the average object lifespan, which results in less effective garbage collection. We also find that prolonging lifespan is the direct result of Linux's Completely Fair Scheduler due to its round-robin like behavior that can increase the heap contention between the application threads. Instead, if we use pseudo first-in-first-out to schedule application threads in large multicore systems, the garbage collection scalability is significantly improved while the time spent in garbage collection is reduced by as much as 21%. The average execution time of the 24 Java applications used in our study is also reduced by 11%. Based on this observation, we propose two approaches to optimally select scheduling policies based on application scalability profile. Our first approach uses the profile information from one execution to tune the subsequent executions. Our second approach dynamically collects profile information and performs policy selection during execution.

Modern Java applications employ multithreading to improve performance by harnessing execution parallelism available in today’s multicore processors. However, as the numbers of threads and processing cores are scaled up, many applications do not achieve the desired level of performance improvement. In this paper, we explore two factors, lock contention and garbage collection performance that can affect scalability of Java applications. Our initial result reveals two new observations. First, applications that are highly scalable may experience more instances of lock contention than those experienced by applications that are less scalable. Second, efficient multithreading can make garbage collection less effective, and therefore, negatively impacting garbage collection performance.

Automating the conversion of human-readable HTML tables into machine-readable relational tables will enable end-user query processing of the millions of data tables found on the web. Theoretically sound and experimentally successful methods for index-based segmentation, extraction of category hierarchies, and construction of a canonical table suitable for direct input to a relational database are demonstrated on 200 heterogeneous web tables. The methods are scalable: the program generates the 198 Access compatible CSV files in ~0.1s per table (two tables could not be indexed).

HTML tables represent a significant fraction of web data. The often complex headers of such tables are determined accurately using their indexing property. Isolated headers are factored to extract category hierarchies. Web tables are then transformed into a canonical form and imported into a relational database. The proposed processing allows for the formulation of arbitrary SQL queries over the collection of induced relational tables.

Most chip-multiprocessors nowadays adopt a large shared last-level cache (SLLC). This paper is motivated by our analysis and evaluation of state-of-the-art cache management proposals which reveal a common weakness. That is, the existing alternative replacement policies and cache partitioning schemes, targeted at optimizing either locality or utility of co-scheduled threads, cannot deliver consistently the best performance under a variety of workloads. Therefore, we propose a novel adaptive scheme, called CLU, to interactively co-optimize the locality and utility of co-scheduled threads in thread-aware SLLC capacity management. CLU employs lightweight monitors to dynamically profile the LRU (least recently used) and BIP (bimodal insertion policy) hit curves of individual threads on runtime, enabling the scheme to co-optimize the locality and utility of concurrent threads and thus adapt to more diverse workloads than the existing approaches. We provide results from extensive execution-driven simulation experiments to demonstrate the feasibility and efficacy of CLU over the existing approaches (TADIP, NUCACHE, TA-DRRIP, UCP, and PIPP).

Correct segmentation of a web table into its component regions is the essential first step to understanding tabular data. Our algorithmic solution to the segmentation problem relies on the property that strings defining row and column header paths uniquely index each data cell in the table. We segment the table using only "logical layout analysis" without resorting to any appearance features or natural language understanding. We start with a CSV table that preserves the 2-dimensional structure and contents of the original source table (e.g., an HTML table) but not font size, font weight, and color. The indexing property of table headers implies a four-quadrant partitioning of the table about a minimum index point. The algorithm finds the index point through an efficient guided search. Experimental results on a 200-table benchmark demonstrate the generality of the algorithm in handling a variety of table styles and forms.

Shared last-level caches (SLLCs) on chip-multiprocessors play an important role in bridging the performance gap between processing cores and main memory. Although there are already many proposals targeted at overcoming the weaknesses of the least-recently-used (LRU) replacement policy by optimizing either locality or utility for heterogeneous workloads, very few of them are suitable for practical SLLC designs due to their large overhead of log associativity bits per cache line for re-reference interval prediction. The two recently proposed practical replacement policies, TA-DRRIP and SHiP, have significantly reduced the overhead by relying on just 2 bits per line for prediction, but they are oriented towards managing locality only, missing the opportunity provided by utility optimization.

We present a combined hardware-software based approach to scan-chain diagnosis, when the outcome of a test may be affected by system faults occurring in the logic out-side of the scan chain. For the hardware component we adopt the double-tree scan (DTS) chain architecture, which has previously been shown to be effective in reducing power, volume, and application time of tests for stuck-at and delay faults. We develop a version of flush test which can resolve a multiple fault in a DTS chain to a small number of suspect candidates. Further resolution to a unique multiple fault is enabled by the software component comprising of fault simulation and analysis of the response of the circuit to test patterns produced by ATPG. Experimental results on benchmark circuits show that near-perfect scan-chain diagnosis for multiple faults is possible even when a large number of random system faults are injected in the circuit.

We present a method based on header paths for efficient and complete extraction of labeled data from tables meant for humans. Although many table configurations yield to the proposed syntactic analysis, some require access to semantic knowledge. Clicking on one or two critical cells per table, through a simple interface, is sufficient to resolve most of these problem tables. Header paths, a purely syntactic representation of visual tables, can be transformed ("factored") into existing representations of structured data such as category trees, relational tables, and RDF triples. From a random sample of 200 web tables from ten large statistical web sites, we generated 376 relational tables and 34,110 subject-predicate-object RDF triples.

We describe a component of a document analysis system for constructing ontologies for domain-specific web tables imported into Excel. This component automates extraction of the Wang Notation for the column header of a table. Using column-header specific rules for XY cutting we convert the geometric structure of the column header to a linear string denoting cell attributes and directions of cuts. The string representation is parsed by a context-free grammar and the parse tree is further processed to produce an abstract data-type representation (the Wang notation tree) of each column category. Experiments were carried out to evaluate this scheme on the original and edited column headers of Excel tables drawn from a collection of 200 used in our earlier work. The transformed headers were obtained by editing the original column headers to conform to the format targeted by our grammar. Forty-four original headers and their reformatted versions were submitted as input to our software system. Our grammar was able to parse and the extract Wang notation tree for all the edited headers, but for only four of the original headers. We suggest extensions to our table grammar that would enable processing a larger fraction of headers without manual editing.

As the Memory Wall remains a bottleneck for Chip Multiprocessors (CMP), the effective management of CMP last level caches becomes of paramount importance in minimizing expensive off-chip memory accesses. For the CMPs with private last level caches, Cooperative Caching (CC) has been proposed to enable capacity sharing among private caches by spilling an evicted block from one cache to another. But this eviction-driven CC does not necessarily promote the cache performance since it implicitly favors the applications full of block evictions regardless of their real capacity demand. The recent Dynamic Spill-Receive (DSR) paradigm improves CC by prioritizing applications with higher benefit from extra capacity in spilling blocks. However, the DSR paradigm only exploits the coarse-grained application-level difference in capacity demand, making it less effective as the non-uniformity exists at a much finer level. This paper (i) highlights the observation of cache set-level non-uniformity of capacity demand, and (ii) presents a novel L2 cache design, named SNUG (Set-level Non-Uniformity identifier and Grouper), to exploit the fine-grained non-uniformity to further enhance the effectiveness of cooperative caching. By utilizing a per-set shadow tag array and saturating counter, SNUG can identify whether a set should either spill or receive blocks; by using an index-bit flipping scheme, SNUG can group peer sets for spilling and receiving in an flexible way, capturing more opportunities for cooperative caching. We evaluate our design through extensive execution-driven simulations on Quad-core CMP systems. Our results show that for 6 classes of workload combinations our SNUG cache can improve the CMP throughput by up to 22.3%, with an average of 13.9% over the baseline configuration, while the state-of-the-art DSR scheme can only achieve an improvement by up to 14.5% and 8.4% on average.

In a scan-based test architecture, the scan power and and test data volume can be reduced by utilizing a double tree scan (DTS) architecture. This paper presents a novel hardware implementation of the DTS architecture and compares the hardware overhead with the conventional scan architecture. The implementation proposed utilizes a clock structure which greatly decreases the number of clocked flip-flops and thereby reduces power consumption. A test chip is designed and fabricated in a 0.5 μm CMOS technology to verify the power saving properties of the architecture.

Efficient management of last level caches (LLCs) plays an important role in bridging the performance gap between processor cores and main memory. This paper is motivated by two key observations, based on our study of LLCs: 1) the capacity demand is highly non-uniform and dynamic at the set level, and 2) neither spatial nor temporal LLC management schemes, working separately as in prior work, can consistently and robustly deliver the best performance under different circumstances. Therefore, we propose a novel adaptive scheme, called STEM, which concurrently and dynamically manages both spatial and temporal dimensions of capacity demands at the set level. In the proposed scheme, a set-level monitor captures the temporal and spatial capacity demands of individual working sets and judiciously pairs off sets with complementary capacity demands so that the underutilized set in each pair can cooperatively cache the other's victim blocks. The controller also decides on the best temporal sharing patterns for the coupled sets in the event of inter-set space sharing. Further, if the LLC controller cannot find a complementary set for a particular set, STEM can still decide on the best set-level replacement policy for it. Our extensive execution-driven simulation data shows that the proposed scheme performs robustly and consistently well under various conditions.

Test power, volume, and time are the major test cost parameters that must be minimized while achieving the desired level of fault coverage. Unlike prior research in delay fault testing that has focused on at most two test cost parameters, the hybrid (LOS+LOC) scheme proposed here simultaneously considers all three cost parameters and achieves better fault coverage than prior schemes, as demonstrated by experimental results. A factor of (n/logn) reduction in test power is achieved by the use of a nonlinear double-tree-scan (DTS) structure instead of linear scan chain of length n. Concomitantly, by exploiting the permutation feature of DTS, whereby the same test data can be loaded in multiple ways, we also achieve substantial reductions in the test-data volume. By incorporating the Illinois scan (ILS) within this framework, we minimize not only the test time but also achieve further reductions in test-data volume.

A persistent flaw in the evaluation of page segmentation algorithms is examined.

A new symbolic approach models the sensitization paths to selected primary output(s) as Boolean equations, with satisfying solutions representing the set of all sources of single and multiple sensitizations in the circuit. The paper discusses two applications of this idea: model-free fault diagnosis and input sensitization analysis.

For performance-critical microprocessors, efficient test-selection methods are needed for reusing a subset of functional validation tests to detect manufacturing defects. Our new input/output transition fault-coverage metric (TRIO) at the register-transfer level is shown to perform much better than current metric in test selection at only an incrementally higher computational cost. TRIO may also be used for testability analysis early in the design cycle

Compact set of 3-valued test vectors for random pattern resistant faults are covered in multiple test passes. During a pass, its associated test cube specifies certain bits in the scan chain to be held fixed and others to change pseudo -randomly. We propose an algorithm to find a small number of cubes to cover all the test vectors, thus minimizing total test length. The test-cube finding algorithm repeatedly evaluates small perturbations of the current solution so as to maximize the expected test coverage of the cube. Experimental results show that our algorithm covers the test vectors by test cubes that are one to two orders of magnitude smaller in number with a much smaller increase in the percentage of specified bits. It outperforms comparable schemes reported in the literature

A Geographic Information System (GIS) populated with disparate data sources has multiple and different representations of the same real-world object. Often, the type of information in these sources is different, and combining them to generate one composite representation has many benefits. The first step in this conflation process is to identify the features in different sources that represent the same real-world entity. The matching process is not simple, since the identified features from different sources do not always match in their location, extent, and description. We present a new approach to matching GIS features from disparate sources. A graph theoretic approach is used to model the geographic context and to determine the matching features from multiple sources. Experiments on implementation of this approach demonstrate its viability.

In a scan-based system with a large number of flip-flops, a major component of power is consumed during scan-shift and clocking operation in test mode. In this paper, a novel scan-path architecture called double-tree scan (DTS) is proposed that drastically reduces the scan-shift and clock activity during testing. The inherent combinatorial properties of double-tree structure are employed to design the scan architecture, clock gating logic, and a simple shift controller. The design is independent of the structure of the circuit-under-test (CUT) or its test set. It provides a significant reduction both in instantaneous and average power needed for clocking and scan-shifting. The architecture fits well to built-in self-test (BIST) scheme under random testing, as well as to deterministic test environment.

A single-parameter text-line extraction algorithm is described along with an efficient technique for estimating the optimal value for the parameter for individual images without need for ground truth. The algorithm is based on three simple tree operations, cut, glue and flip. An XY-tree representing the segmentation is incrementally transformed to reflect a change in the parameter while intrinsic measures of the cost of the transformation are used to detect when specific tree operations would cause an error if they were performed, allowing these errors to be avoided. The algorithm correctly identified 98.8% of the area of the ground truth bounding boxes and committed no column bridging errors on a set of 97 test images selected from a variety of technical journals.

In simulation based design verification, deterministic or pseudo-random tests are used to check functional correctness of a design. In this paper we present a technique generating tests by specifying the don't care inputs in the functional specifications so as to improve their coverage of both design errors and manufacturing faults. The don't cares are chosen to maximize sensitization of signals in the circuit. The tests generated in this way require only a fraction of pseudo-exhaustive test patterns to achieve a high multiplicity of fault coverage.

The black layer is digitized from a USGS topographic map digitized at 1000 dpi. The connected components of this layer are analyzed and separated into line art, text, and icons in two passes. The paired street casings are converted to polylines by vectorization and associated with street labels from the character recognition phase. The accuracy of character recognition is shown to improve by taking account of the frequently occurring overlap of line art with street labels. The experiments show that complete vectorization of the black line-layer bitmap is the major remaining problem.

A new method is proposed for improving the testability of a finite state machine (FSM) during its synthesis. The method exploits clock control to enhance the controllability and observability of machine states. With clock control it is possible to add new state transitions during testing. Therefore, it is easier to navigate between states in the resulting test machine. Unlike prior work, where clock control is added to the circuit as a post-design step, here, clock control is considered in conjunction with a symbolic scheme for encoding the states of the FSM. The encoding is shown to result in significant reductions in the interstate distances in the benchmark FSM's. Further, the observability of the encoded states can be improved by adding two primary outputs to the circuit such that a fixed input sequence forms a distinguishing sequence for all states. Theoretical results show that for a large class of FSM's, the testability improvements are comparable to those achievable by scan designs. Experimental results show that available test pattern generation tools are able to take advantage of the enhanced testability in producing shorter test sequences, particularly for machines with poor connectivity of states.

We propose a new synthesis technique for finite state machines that improves their testability by disabling the clock to a subset of the flip-flops. Distance-matrix results with and without the clock control demonstrate dramatic improvement in the average and worst-case distances between pairs of states. The experimental results using available sequential ATPG tools further verify that the scheme allows significantly shorter tests to be generated with comparable fault coverage.

Signal probability calculation in circuits where signals are not independent is generally expensive. We show that some correlated signals may be mutually disjoint. In such cases, the probability calculation can be as simple as it is for independent signals. For example, two signals that cannot be simultaneously true are defined as OR-disjoint. If these signals feed an OR gate, the probability of the output being true is simply the sum of the probabilities of inputs being true. We give an implication-based algorithm for identifying disjoint signals. Examples of large adders illustrate how the identification of disjoint signals simplifies the probability calculation.

We present a system for recognizing a large class of engineering drawings characterized by alternating instances of symbols and connection lines. The class includes domains such as flowcharts, logic and electrical circuits, and chemical plant diagrams. The output of the system, a netlist identifying the symbol types and interconnections, may be used for design simulation or as a compact portable representation of the drawing. The automatic recognition task is divided into two stages: 1) domain-independent rules are used to segment symbols from connection lines in the drawing image that has been thinned, vectorized, and preprocessed in routine ways; 2) a drawing understanding subsystem works in concert with a set of domain-specific matchers to classify symbols and correct errors automatically. A graphical user interface is provided to correct residual errors interactively and to log data for reporting errors objectively. The system has been tested on a database of 64 printed images drawn from text books and handbooks in different domains and scanned at 150 and 300 dpi resolution.

The testability of a sequential circuit can be improved by controlling the clock of individual storage elements during testing. We propose several clock control strategies derived from an analysis of the circuit, its S-graph structure, and its function. Through examples we show how the number of clocks affects the circuit's testability. It is shown that if certain flip-flops (FFs) are scanned (or otherwise initialized), the remaining FFs can be controlled and initialized to any arbitrary state using the clock control. We derive a controllability graph and use it to assign clocks to FFs and to schedule the clocks to set the FFs to an arbitrary state during test. Our analysis of sequential benchmark circuits indicates that this could be an attractive scheme for combining partial scan with clock control.

A genetic algorithm (GA) is a robust problem-solving method based on natural selection. Hardware's speed advantage and its ability to parallelize offer great rewards to genetic algorithms. Speedups of 1-3 orders of magnitude have been observed when frequently used software routines were implemented in hardware by way of reprogrammable field-programmable gate arrays (FPGAs). Reprogrammability is essential in a general-purpose GA engine because certain GA modules require changeability (e.g. the function to be optimized by the GA). Thus a hardware-based GA is both feasible and desirable. A fully functional hardware-based genetic algorithm (the HGA) is presented here as a proof-of-concept system. It was designed using VHDL to allow for easy scalability. It is designed to act as a coprocessor with the CPU of a PC. The user programs the FPGAs which implement the function to be optimized. Other GA parameters may also be specified by the user. Simulation results and performance analyses of the HGA are presented. A prototype HGA is described and compared to a similar GA implemented in software. In the simple tests, the prototype took about 6% as many clock cycles to run as the software-based GA. Further suggested improvements could realistically make the HGA 2–3 orders of magnitude faster than the software-based GA.

Column segmentation logically precedes OCR in the document analysis process. The trainable algorithm XYCUT relies on horizontal and vertical binary profiles to produce an XY-tree representing the column structure of a page of a technical document in a single pass through the bit image. Training against ground truth adjusts a single, resolution independent, parameter using only local information and guided by an edit distance function. The algorithm correctly segments the page image for a (fairly) wide range of parameter values, although small, local and repairable errors may be made, an effect measured by a repair cost function.

We present a complete system for recognizing a large class of symbolic engineering drawings that includes flowcharts, chemical plant diagrams, and logic & electrical circuits. The output of the system, a netlist identifying the symbol types and interconnections, may be used for design verification or as a compact portable representation of the drawing. The automatic recognition task is done in two stages: (1) domain-independent rules segment symbols from connection lines in the preprocessed drawing image and (2) an understanding subsystem makes use of a set of domain-specific matchers to classify symbols and correct errors automatically. A graphical user interface is provided to correct residual errors interactively. The system has been tested on a large database of printed images drawn from four different domains.

Abstract Programming applications in computer‐aided design of VLSI are difficult on parallel architectures, especially pipelined implementations derived from their sequential counterparts by algorithmic partitioning. The difficulty is primarily due to lack of good program development environments and tools. Our solution, applicable to message‐passing architectures, is based upon a definition of a broad class of non‐linear pipeline configurations and an asynchronous data‐driven model for pipeline stage interactions. It provides object‐oriented definitions of stages and interconnecting channels. These objects are embedded in C++ so that the correctness of application programs can be tested on a workstation in a simulated environment. The simulation is instrumented to provide data useful in assessing relative computational loading and balancing of stages. Thus a large part of program development can take place in the environment of a workstation familiar to the programmer. A non‐trivial application is developed to illustrate these ideas.

An implementation of a design for testability model for sequential circuits is presented. The flip-flops in a sequential circuit are partitioned to reduce the number of cycles and the path lengths in each partition, thereby reducing the complexity of test generation. The implementation includes a Podem-based test generator. Preliminary results using the Contest sequential test generator are presented.>

A method for extracting alternating horizontal and vertical projection profiles are from nested sub-blocks of scanned page images of technical documents is discussed. The thresholded profile strings are parsed using the compiler utilities Lex and Yacc. The significant document components are demarcated and identified by the recursive application of block grammars. Backtracking for error recovery and branch and bound for maximum-area labeling are implemented with Unix Shell programs. Results of the segmentation and labeling process are stored in a labeled x-y tree. It is shown that families of technical documents that share the same layout conventions can be readily analyzed. Results from experiments in which more than 20 types of document entities were identified in sample pages from two journals are presented.>

It is shown that the known methods of field reject ratio prediction are not accurate since they fail to realistically model the process of testing. The authors model the detection of a fault by an input test vector as a random event. However, the detection of a fault may be delayed for various reasons: the fault may be detectable only by application of a sequence of vectors or it may not have been targeted until later. In the statistical model, a fault is characterized by two parameters: a per-vector detection probability and an integer-valued latency. Irrespective of the detection probability, the fault cannot be detected by a vector sequence shorter than its latency. The circuit is characterized by the joint distribution of latency and detection probability over all faults. This distribution, obtained by applying the Bayes' rule to the actual test data, allows computations the field reject ratio. The sensitivity of this approach to variations in the measured parameters is also investigated.>

Abstract: Detection of a fault in a sequential circuit requires a sequence of test vectors. This se-quence activates the fault and propagates the effect of the fault to a primary output. To accomplish this, the test sequence must set flip-flops through a series of states. Unlike a combinational circuit, many faults in a sequential circuit cannot be detected by a sin-, gle vector. We propose a statistical model in which. a fault is characterized by two parameters: a per-vector detection probability and an integer-valued la-. tency. Irrespective of its detection probability, the fault cannot be detected by a vector sequence shorter than the latency. A joint distribution of the latency and detection probability over all the failed chips is thus obtained. Using the new model, an analysis o:f chip failure data to predict actual yield and reject ra-tio is given. For a large-volume CMOS chip, tested by vectors having 99.7 % fault coverage, this analysis gives a reject ratio of 43 parts per million that is be-lieved to be in close agreement with the field data. 1

The authors report on an experiment to verify the accuracy of reject ratio predictions by the available approaches. The data collection effort includes instrumenting the wafer probe test to obtain chip failures as a function of applied vectors and running a fault simulator to obtain the cumulative fault coverage of these vectors. The accuracy of reject ratio predictions is judged by assuming earlier stopping points for the wafer probe, thereby gaining a measure of confidence in the final predicted value. The results of five different analyses are reported for over 70000 tested dies of a CMOS VLSI device. The five methods discussed predicted values for the reject ratio that vary by an order of magnitude at high values of fault coverage. It is shown that, with only an incremental effort during wafer probe, data collection that can be used to compare the relative accuracy of different models over a range of fault coverage is possible.>

A relation between the average fault coverage and circuit testability is developed. The statistical formulation allows computation of coverage for deterministic and random vectors. The following applications of this analysis are discussed: determination of circuit testability from fault simulation, coverage prediction from testability analysis, prediction of test length, and test generation by fault sampling.>

Test sequence length is an effective measure of testability of a sequential circuit. The lower the bound on the length, the more testable the circuit is. A graph-theoretic approach is used to compute the bound on test sequence length for any sequential circuit. The condensation of the graph is found by collapsing the strongly connected components into single nodes. By analyzing each stem region, it is possible to compute the bound on test sequence length for the entire circuit. The time complexity of the procedure is O(n/sup 2/), where n is the number of nodes in the circuit graph. The bounds of the individual submachines can be used in test generation, scan design, and built-in self-test design. Three design rules are specified to yield circuits with lower test sequence bounds.>

The parity testability of a single output is related to its partition in terms of maximal supergates, and a scheme is proposed for making an untestable circuit parity testable by augmenting its maximal supergates. Only a small amount of extra logic and a single external test-mode pin are required to complete the design. The test procedure is simple, and the hardware overhead is low.>

The authors consider a class of AND-OR tree circuits and study their response to random-pattern inputs as the depth of the tree is allowed to increase indefinitely. Each binary input of a circuit is independently chosen to be one (zero) with probability x (1-x). The logic of the circuit determines the probability of success (one) at the output as a monotonically increasing S-shaped function of x called the probability transfer function. The probability transfer function of an AND-OR tree is shown to have just one interior fixed point (with respect to changes in depth of the tree) in the

The performance of a fast fault simulation algorithm for combinational circuits, such as the critical-path-tracing method, is determined primarily by the efficiency with which it can deduce the detectability of stem faults (stem analysis). A graph-based approach to perform stem analysis is proposed. A dynamic data structure, called the criticality constraint graph, is used during the backward pass to carry information related to self-masking and multiple-path sensitization of stem faults. The structure is updated in such a way that when stems are reached, their criticality can be found by looking at the criticality constraints on their fanout branches. Compared to the critical-path-tracing method, the algorithm is exact and does not require forward propagation of individual stem faults. Several examples which illustrate the power of the algorithm are given. Preliminary data on an implementation are also provided.>

A substitution cipher consists of a block of natural language text where each letter of the alphabet has been replaced by a distinct symbol. As a problem in cryptography, the substitution cipher is of limited interest, but it has an important application in optical character recognition. Recent advances render it quite feasible to scan documents with a fairly complex layout and to classify (cluster) the printed characters into distinct groups according to their shape. However, given the immense variety of type styles and forms in current use, it is not possible to assign alphabetical identities to characters of arbitrary size and typeface. This gap can be bridged by solving the equivalent of a substitution cipher problem, thereby opening up the possibility of automatic translation of a scanned document into a standard character code, such as ASCII. Earlier methods relying on letter n-gram frequencies require a substantial amount of ciphertext for accurate n-gram estimates. A dictionary-based approach solves the problem using relatively small ciphertext samples and a dictionary of fewer than 500 words. Our heuristic backtrack algorithm typically visits only a few hundred among the 26! possible nodes on sample texts ranging from 100 to 600 words.

Earlier approaches to random compact testing use a random pattern generator which depends on the combinational function under test and a circuit signature which remains the same independent of the circuit. In this correspondence we analyze the performance of a new scheme in which the pattern generator is simple and independent of the function being tested but the circuit signature is chosen to be a coefficient from the Rademacher-Walsh (RW) spectrum of the function under test. The analysis provides guidelines for choosing an RW coefficient, a test length, and an error tolerance so as to minimize the probabilities of rejecting a good unit or accepting a faulty one.

The results of production test on LSI wafers are analyzed to determine the parameters of the yield equation. Recognizing that a physical defect on a chip can produce several logical faults, the number of faults per defect is assumed to be a random variable with Poisson distribution. The analysis provides a relationship between the yield of the tested fraction of the chip area and the cumulative fault coverage of test patterns. The parameters of the yield equation are estimated by fitting this relation to the measured yield versus fault coverage data.

A simplified method is presented to calculate moments of failure time and residual lifetime of a fault-tolerant system. The method is based on recent results in queueing theory. Its effectiveness is illustrated by considering a dual repairable system from the literature.

This correspondence generalizes Hayes' recent ideas for generating an optimal transition write sequence which forms the "backbone" of his algorithm for testing semiconductor RAM's for pattern-sensitive faults. The generalization, presented in graph theoretic terms, involves two sequential steps. The frmst step results in assigning of a "color" to each memory cell. In the second step, each color is defined as a distinct sequence of bits representing the sequence of states assumed by the correspondingly colored cell. The constraints imposed at each step lead to interesting and general problems in graph theory: the standard graph coloring problem in the first step, and a path projection problem from a binary m-cube to a subcube in the second step. Applications to arbitrary k-cell neighborhoods, and particularly to three-cell neighborhoods are shown.

Fan-out-free networks of AND, OR, NOT, EXOR, and MAJORITY gates are considered. Boolean functions for which such networks exist are defined to be fan-out free. The paper solves the following problems regarding the fan-out-free networks and functions.

The problem of fault detection and location in tree networks of two input EXCLUSIVE-OR (EOR) gates is considered. The fault model assumes that an EOR gate can change to any other function of its two inputs except the equivalence function. An efficient procedure for single fault location is presented. In the worst case the number of tests necessary to locate single faults is bounded by a linear function of the number of input variables. Constructive upper bounds are obtained for the number of tests to detect multiple faults. Optimality of these bounds is argued and extension of results to other types of networks is considered.