As CMOS technology continues to scale, the associated reduction in device reliability margins has made accurate reliability evaluation a critical component of digital circuit design. Traditional methods typically assess reliability based on the average behavior of multiple input vectors (MIVs), while neglecting the significant variation introduced by individual input vector (IIV). In practice, different IVs often exhibit heterogeneous reliability distributions, and in sequential circuits with temporal correlation, these differences may span several orders of magnitude. This paper proposes a probabilistic injection framework for reliability analysis that explicitly considers input correlation in a sequential circuit. The method enables both fine-grained evaluation for each IIV and global assessment across MIVs, thereby offering a comprehensive understanding of not only average circuit reliability but also reliability bounds under specific input conditions. Experimental results on ISCAS’89, ITC’99, IWLS’05 and reference benchmark circuits demonstrate that the proposed approach achieves higher accuracy and greater stability compared to traditional methods.

For quantized deep neural networks widely deployed on hardware-accelerated platforms, bit-flip attacks (BFAs) have become a serious security threat because they can cripple or hijack model inference by modifying only a few bits. To this end, we propose KHAD (K-Hop and Activation-aware Defense), a unified, minimally intrusive defense framework that fuses k-hop propagation with activation statistics to precisely assess neuronal criticality and adaptively partitions neurons into three categories, to which it applies lightweight strategies: elastic boundary rectification, soft limiting with least significant bit masking, and range tightening with orthogonal diffusion, respectively. We conduct performance experiments across datasets of different scales and multiple models. The results show that, while exerting only a very small impact on clean accuracy (e.g., a decrease of 1.73% for ResNet-32 on CIFAR-100), KHAD exhibits strong defensive capability. Under untargeted attacks, it increases the minimum number of bit flips required to break the model by 5.6× to 14.3×; under targeted attacks, it effectively reduces the attack success rate (ASR) to 1.40%–15.60%. Moreover, the method can be fully deployed at model export time, yielding extremely low runtime overhead across CNN and Transformer architectures. These results indicate that, compared with global redundancy-based defenses, KHAD combines structural propagation properties with data-driven activity to precisely identify and block a small number of high-leverage propagation paths, trading a slight cost for substantial robustness gains.

Stealthy Bit-Flip Attacks, which manipulate DNN predictions by altering a few hardware-level weights, pose a severe threat to safety-critical applications. To address this threat, we propose the Dual-Mask Dynamic Defense (DMDD), whose core idea is to proactively and dynamically disrupt the static paths that attackers construct by exploiting model redundancy at inference time. DMDD’s defense is accomplished by two synergistic online mechanisms: 1) At the intermediate layers, Dual-mask Dynamic Neuron Pruning (DDNP) first employs an "Efficiency Mask" to prune task-irrelevant redundant neurons for efficiency gains, and then uses a "Security Mask" to sever potential attack paths by monitoring statistical anomalies in neuron behavior. 2) At the final layer, Dynamic Connection Purification (DCP) is activated to perform semantic-level filtering. To ensure the model can tolerate this online restructuring and the effects of residual attack paths, we also designed a complementary offline Pruning-aware Robustness Training (PART) strategy to enhance the model’s pruning tolerance and enforce larger inter-class distances. Unlike traditional defenses, DMDD transforms defense overhead into performance gains, achieving security enhancement with "negative computational overhead." Experiments show that DMDD can suppress the Attack Success Rate (ASR) of mainstream attacks like TBFA and TA-LBF from nearly 100% to below 15%, while simultaneously reducing the model’s computational load (FLOPs) by 26%-42%, providing an efficient and practical solution for secure DNN deployment in resource-constrained scenarios.

Hardware Trojans (HTs) present significant security threats to integrated circuits. Detecting and locating HTs is crucial for mitigating these threats. Thus, this article proposes a method called HTs-GCN, which utilizes a graph convolutional network (GCN) to identify HTs. First, it extracts two novel features of gate nodes using a depth-first search strategy and topological logical analysis to enrich the feature information of circuit nodes. Second, through a message-passing mechanism, it designs a local feature aggregation method based on the GCN and a global feature fusion method based on an attention mechanism to improve the representation capability of circuit node features. Then, leveraging the concept of stochastic gradient descent and incorporating mini-batch oversampling and under-sampling techniques, it employs a dataset imbalance handling method to address the scarcity of HT nodes in circuits. These approaches significantly enhance the distinguishability between gate nodes with HTs and other gate nodes while reducing computational complexity. Experimental results indicate that HTs-GCN outperforms the recently proposed NHTD-GL method in terms of recall: it achieves approximately 7.8% points higher recall while maintaining similar accuracy. HTs-GCN demonstrates exceptional generalizability, with an average recall and accuracy of 93.0% and 100%, respectively, on infrequently used circuits in the Trust-Hub benchmark. In addition, on the TRIT-TC benchmark, HTs-GCN achieves excellent average true positive rate (TPR) and true negative rate (TNR) of 95.1% and 94.4%, respectively. Furthermore, HTs-GCN exhibits robust performance under gate modification attacks, with average TPR and TNR reaching 82.1% and 92.5%, respectively.

Persistent Fault Analysis(PFA) is a powerful analysis technique proposed in CHES 2018, which utilizes those faults that are injected before execution and persist throughout the encryption. However, when it is applied to the block cipher which has multiple S-boxes, the key cannot be recovered in just one attack. The adversary has to conduct the fault attack several times and inject faults into all the distinct S-boxes. In this paper, we proposeKey Schedule Guided Persistent Fault Attack(KGPFA), which utilizes the key schedule to guide the fault injection and fault analysis. By analyzing the key schedule, KGPFA exploits the relations between the key leakages caused by the same faulty S-box in various rounds. It can reduce the number of attacks and the number of faults required to recover the key. Our major contributions are twofold. Firstly, in the fault injection step, we provideKey Schedule Guided Persistent Fault Injection(KGPFI) strategies to reduce the number of attacks and the number of faults under the assumption of both ciphertext-only and known-plaintext attacks. Secondly, in the fault analysis step, as our target ciphers are Feistel-based, we propose theIneffective Algebraic Persistent Fault Analysis(IAPFA) to extend the usage ofAlgebraic Persistent Fault Analysis(APFA) in the ineffective persistent fault setting. To demonstrate the effectiveness of our technique, we apply KGPFA to four widely used block ciphers with multiple S-boxes, DES, 3DES, LBlock, and Camellia. In our experiment, in the ciphertext-only attack, the key of DES can be recovered with 300 ineffective ciphertexts (coresponding to 827 ciphertexts) and four faulty S-boxes within 12.18min. Under the assumption of known-plaintext, the key of DES is recovered within two faulty S-boxes in 2.34h. For LBlock, the key is recovered with two faulty S-boxes and 100 ineffective ciphertexts (coresponding to 6211 ciphertexts) in 1.16min.

Hardware Trojans (HTs) pose a significant threat to the security of integrated circuits(ICs). Measuring the vulnerability of ICs to HT insertions is crucial for enhancing design security, thereby mitigating potential security risks. This paper proposes a novel vulnerability measurement method for ICs against HT insertions based on node co-activation analysis. The method first transforms the circuit structure into a graph representation, where nodes represent circuit interconnections, and edges represent circuit components, using graph learning (GL) techniques. Next, it calculates the logical probability distribution and logic flip probability for each circuit node using simulation methods. By combining an adaptive threshold filtering strategy, the method identifies suspicious nodes in the circuit using simulation methods combined with an adaptive threshold screening strategy to identify suspicious nodes in circuits. Subsequently, it computes the joint probabilities of pairs of suspicious nodes that simultaneously exhibit rare logic values based on simulation results. Finally, the vulnerability of the circuit to HT insertions is quantified by evaluating the co-activation between pairs of suspicious nodes. Experimental results demonstrate the effectiveness, efficiency, and generalization capability of the proposed method.

Accurate and efficient identification of reliability-critical paths (RCPs) not only facilitates fault localization and troubleshooting but also allows circuit designers to improve circuit reliability at a low cost. This article proposes a local and global adjacency probability matrix-based approach (LGAPM) to quickly and efficiently identify RCPs of combinational logic circuits. The approach reflects the criticality of the overall reliability of the circuit as well as the local criticality of gates in the path. In addition, we design a pruning-based method to accelerate RCP identification in large-scale circuits. The experimental results of the LGAPM on all 74 series circuits, ISCAS-85, and partial EPFL benchmark circuits show that the 74181 circuit with a minimum of 17 paths and the EPFL-remainder10 circuit with a maximum of 8.081 × 108paths take times of about 0.18s and 33931.04s, respectively. The average accuracy on small and medium-scale circuits is 94.24%, and the average stability on all-size circuits is 86.19%. Compared to the SAT-based method, hill-climbing algorithm, and random method, LGAPM’s metrics are superior and more appropriate for large-scale circuits. The overall circuit reliability can be improved from 0.7726 to 0.9238 on average by hardening a tiny number of gates in the identified the most RCPs and the average cost savings is 4.08 times over random hardening methods.

The identification of reliability-critical input vectors (RCIVs) is vital in the assessment and prediction of reliability boundaries for logic circuits. This article introduces an approach grounded in association rule analysis (ARA) to swiftly and efficiently identify RCIVs in both combinational and sequential circuits. The utilization of the ARA model for validating the circuit’s associated primary inputs enhances accuracy while simultaneously reducing the complexity of RCIVs identification. Orienting the generation of new samples with associated inputs expedites the identification process. Quantifying circuit complexity enables the adaptive assignment of algorithmic parameters to circuits of diverse sizes. The construction of input sets facilitates a precise evaluation of the reliability of individual input vectors in sequential circuits. Experimental results on benchmark circuits illustrate that this approach achieves a mean accuracy of 0.9952, with Monte Carlo (MC) method serving as the reference, for small and medium-sized circuits, and require only 20.71% of MC’s time overhead. The average coverage of 0.9884 surpasses the reference method by 1.8 times. The stability is 4.35 times higher with the random method on large scale circuits with 224,624 gates and 6,642 primary inputs. Circuit designers can swiftly ascertain the average reliability and reliability boundaries of a circuit by using this approach for RCIVs identification. By applying optimizations of the identified RCIVs to expedite convergence and mitigate fluctuations, the influence of these RCIVs can be minimized in reliability evaluation and testing.

The input vector-oriented reliability estimation of sequential circuits plays an important role in predicting their reliability boundaries and identifying their reliability-critical gates. This article presents an input vector-oriented programmable method based on fanout-source tracking and reduction for the reliability evaluation of sequential circuits. In the proposed method, fanout-source tracking is introduced to track fanout sources of a computing node to determine the fanout sources affecting the node output signals. An iterative reduction method is presented to eliminate duplicate calculations caused by fanout reconvergences without reducing the accuracy. A dynamic fanout relevance-keeping-based calculation method is used to approximate the trend probability vector of low-priority nodes outputting “0” and “1” to accelerate the calculations at a small accuracy loss. A complexity-accuracy tradeoff method based on a programmable fanout source length is designed to facilitate reasonable calculations as needed. Experimental results on large-scale circuits show that the average relative error of the proposed method is 1.01% with Monte Carlo (MC) as a reference. Moreover, the proposed method is 4,308.13 times faster than the MC on average, but its average memory cost is 3.40 higher than that of the MC model. Compared with similar methods, the proposed method not only is suitable for large-scale circuits and performs better in accuracy, but also enables programmable computation to dynamically balance the tradeoff between accuracy and speed as actual needed, resulting in better applicability and scalability.

Identifying the critical paths is crucial to reducing the complexity of performance analysis and reliability calculation for logic circuits. In this article, we propose a method for identifying the critical path in a combination circuit using a reinforcement learning framework to enhance its applicability and compatibility. Initially, we configured the learning environment of the model based on circuit structure information to provide valuable information for decision-making on time. Subsequently, the upper confidence bound applied to trees (UCT) algorithm is employed to construct the behavior decision strategy of the model, which avoids invalid traversal and reduces computing costs. Then, a goal-oriented reward and punishment function is constructed based on the distance from the circuit primary outputs. Finally, based on the parallel computing strategy, we construct an adaptive training method to improve the model’s prediction accuracy by using finite sampling, which speeds up the convergence speed and enhances the quality of the model. Experimental results on benchmark circuits show that, with the functional timing analysis method as the reference, the average accuracy of the proposed method is as high as 99.39% and the single average calculation speed is 18.07 times faster than that of the reference method. Compared with the Monte Carlo model, the proposed method has a higher critical path hit rate, and the average calculation speed is 928.75 times faster.

In nanometric integrated circuits, to harden reliability-critical gates (RCGs) is an important step to improve overall circuit reliability at a low cost. To locate RCGs quickly and efficiently is a key prerequisite for selective hardening at the early stage of circuit design. This article develops a new approach for locating RCGs for multiple input vectors in combinational circuits, using an input vector-oriented pruning technology to identify RCGs, and a sensitivity-based algorithm to measure the criticality of gate reliability (CGR) for each identified RCG. To accelerate the location of RCGs, a feedback-based algorithm mines the accumulated simulation data for each RCG, and a grouping algorithm handles RCGs with similar CGR in the stage of convergence checking. Simulations on 74-series and ISCAS 85 benchmark circuits show that the average accuracy of the proposed method is 0.986 with Monte–Carlo (MC) as the reference and it is 7181 times faster than the MC model. Also, this method performs better than other approximate algorithms in terms of location accuracy and time overhead.

Redundancy-reliability calculation for deep neural networks is of great importance for their lightweight operation. This article proposes a method for calculating the redundancy-reliability of convolutional neural networks (CNNs) based on strip-median attributes. First, based on the common cause principle, an input-sample-oriented reliability calculation method with automatic boundary detection is constructed to measure the network reliability differences caused by normal classification boundary changes. Next, the adaptive clustering algorithm is used and combined with strip-median attributes to identify the redundant strips of each convolutional layer (CONV) in the networks. Then, based on the central limit theorem and the Pauta criterion, a fault injection method with adaptive convergence ability is constructed to effectively calculate the soft-error-oriented redundancy-reliability of CNNs. The tests of multiple widely used CNNs with multiple datasets showed that with the results of the Monte Carlo (MC) model as the references, the reliability calculation accuracy of the proposed method was approximately 0.9834 and was 3.0% higher than that of the logical flips at bit level (LFBL) method. Additionally, the identification accuracy of the proposed method for redundant nodes in CNNs was better than that of the HRank method and the$1 \times N$pruning method, by average factors of approximately 14.32 and$1.55\times $, respectively. Furthermore, the redundant protection and the adaptive layer geometric center searching mechanism designed by the proposed method were effective. Thus, the proposed method can effectively achieve a one-to-one correspondence between the redundancy and reliability of CNNs.

Reliable circuits help prevent artificial intelligence (AI) systems from being corrupted by the soft errors occurred in memories or combinational circuits, which promotes the development of AI security. However, it is a great challenge to measure the reliability of combinational circuits at register transfer level (RTL) rapidly and efficiently. In this paper, a new fast and accurate computational model based on stochastic computation (SC) is presented to meet these objectives. In the proposed approach, the circuit netlists at RTL are parsed to satisfy the requirements of SC on the bitstream structure of the circuits, and then a Sobol sequence-based algorithm for generating uniform non-Bernoulli sequences is built to reduce the random fluctuations occurred in probability calculations. After that, an adaptive algorithm based on a MAX–MIN ant system is constructed using graphics processing unit-based parallel schemes to greatly accelerate the calculation. The experimental results validate our proposed technique, showing that this approach was approximately 51 and 42 times faster than the traditional SC approach and the stochastic computational model (SCM), respectively; its required sequence length was approximately 1.66 times shorter than that of the traditional SC approach, and its relative error was two times smaller than that of the SCM.

Accurate and effective localization of reliability-critical gates (RCGs) is one of the important prerequisites for low-cost circuit fault tolerance in the early stages of circuit design. This article introduces an accurate and effective approach for localizing RCGs in combinational logic blocks through a benchmarking technique. In the proposed approach, uniform non-Bernoulli sequences are used to produce a set of input vectors for driving circuits. A full-period linear congruential algorithm is employed to generate a sequence that provides the sampled order for the RCGs to be analyzed. This ensures that each gate in the circuit is treated as fairly as possible. To accelerate the localization process, an input-vector-based pruning technique combined with a counting method is also introduced to identify the specified number of RCGs. Then, the criticality of gate reliability for each RCG is measured through benchmarking. A clustering algorithm carries out the convergence checking for the proposed approach. The performance of the proposed approach was evaluated in terms of accuracy, stability, and time-space overhead by various simulations on 74-series circuits and ISCAS-85 benchmark circuits. The results show that its accuracy is close to that of the Monte Carlo model and its stability is better than that of other approximate methods. Moreover, compared with approximate methods, the time overhead of our approach is advantageous in the presence of similar memory overheads.

The identification of reliability-critical primary input leads (RCPIs) plays an important role in the testing and prediction of reliability boundaries of logic circuits. This article presents a gate-sensitive-attributes-based approach to estimate the criticality of the primary input leads in combinational circuits to their reliability. Oriented to the input vector, a subcircuit-based traversal method marks the critical input leads of each gate in a circuit. Gate-sensitive attributes and a reverse recursive algorithm quantify the effect of each RCPI on circuit reliability under the input vector. A parallel calculation method based on subcircuits with only one primary output reduces the computational complexity to accelerate the calculation process. Similarity-based clustering avoids unnecessary calculations, and a self-adaptive strategy is used to check convergence. Experimental results on benchmark circuits show that the average accuracy of this approach is 0.9634 with Monte Carlo (MC) as the reference and it is 3445 times faster than the MC on average while its average memory cost is 1.67 greater than the MC model. Although the fitness of the worst input vector obtained by other reference methods is 1.09 times better than that of this approach on average, this approach is approximately 21 times faster than that reference method on average.

Owing to the high density, low contrast, deformable cell shapes, low inter-cellular shape and appearance variation, and occlusion of the cells by division or fusion especially in phase-contrast microscopy images, it is still a challenging task to segment cells from the complex background. In this work, we proposed a multi-scale convolution Unet (MC-Unet) for bladder cancer cell segmentation in Phase-Contrast microscopy images. More specifically, the second 3x3 convolution of each layer in the standard Unet is replaced with a multi-scale convolution (MC) block with different kernel sizes, such as 1x1, 3x3, and 5x5. To verify the effectiveness of the proposed method, a series of experiments are conducted on the bladder cancer T24 dataset and the MoNuSeg dataset, and the results shows the proposed MC-Unet can obtain better comprehensive performance than the standard Unet.

The sensitivity of circuit input vectors plays an important role in estimating circuit reliability bounds and identifying reliability-critical gates. Consequently, to effectively calculate the circuit sensitivity for the input vectors is becoming a necessity for nanocircuits, helping circuit designers to select the architecture that best optimizes the tradeoffs between reliability and area power delay. Combining probability signals and employing the iterative strategy presented in Monte Carlo method, this paper proposes an iterative algorithm based on a probabilistic transfer matrix to investigate the circuit sensitivity for the given input vectors, ensuring computational precision and speed. Simulation results on benchmark circuits show that the proposed algorithm is an efficient and accurate method to calculate the sensitivity of the applied input vectors, and that it can be used to improve circuit reliability at a small cost in the early stages of circuit design.