This summary presents a 100 V output hybrid boost converter for an acoustic display driver. The proposed design incorporates two switched-capacitor topologies, the Fibonacci and Dickson topologies, to balance the on-chip area of power switches and the number of off-chip capacitors. The power stage utilizes laterally diffused N-type MOS (LDMOS) devices to enhance overall performance. A stacked active bootstrap circuit is employed to ensure sufficient gate driving voltage in multilevel bootstrapping, thereby preventing forward voltage drops from the passive diode. The converter achieves a voltage conversion ratio (VCR) of $20-40 \times$, with a maximum output voltage of 100 V from an input of $2.5-5 \mathrm{~V}$. It delivers a maximum output power of 2 W, peak efficiency of 86.2%, and a power density of $7.43 \mathrm{~W} / \mathrm{cm}^{3}$.

Analog circuit sizing remains a critical bottleneck in integrated circuit design, requiring extensive manual effort and computational resources. While multi-agent reinforcement learning (MARL) accelerates optimization through parallel agent training, existing approaches rely on manual circuit block clustering that fails to capture functional relationships between parameters. This paper presents ACEMARL, an adaptive clustering framework that automatically discovers functionally similar parameter clusters. ACEMARL integrates Bi-population Covariance Matrix Adaptation Evolution Strategy (BIPOP-CMA-ES), a high-performance evolutionary algorithm, for multi-modal exploration with data-driven clustering, aiming for automatic agent assignment. Experimental validation on amplifier and low-dropout regulators with up to 179 parameters demonstrated 3.3-5.0× faster convergence and 5.7-38.5% Figure-of-Merit (FoM) improvement compared to state-of-the-art (SOTA) block-based methods. The framework reduced confidence interval width by 31.6-60.7% along mean reward trajectories, enabling fully automated analog circuit sizing with improved stability and performance.

Due to the convenience and electrostatic discharge (ESD)-free features, wireless power transfer (WPT) technology has become essential for mobile devices. Conventional WPT solutions use symmetrical inductive couplers with complex structures to enhance misalignment tolerance, while using a large transmitter (TX) coil with a small receiver (RX) coil can increase distance but results in lower power density. On the contrary, we employ in this paper small TX coil and large RX coil for a better tradeoff between power transfer efficiency (PTE), output power and robustness. With detailed analyses, we prove that the small TX large RX configuration outperforms the conventional large TX coil and small RX coil solution and derives the necessary conditions with design procedures for achieving optimal PTE and desired output power. An experimental setup is built to validate the analyses, revealing that the small TX large RX configuration achieves better PTE under the higher output power conditions. Specifically, the system with small TX large RX configuration attains a PTE of 98.7% at an output of 31.29W with an airgap of 10mm.

This article presents a method for the analysis of power supply rejection (PSR) of low-dropout regulators (LDOs), especially for those with a buffer stage. To determine the optimal design combination for each block in an LDO, we analyze and categorize ripple-coupling paths in LDOs with a buffer stage using a small-signal model based on the open-loop PSR concept. High frequency characteristics of the LDO power stage with and without an off-chip load capacitor are also analyzed in detail to extend the proposed method to very high frequencies, and to optimize the PSR performance at high frequencies. And then the co-design of open-loop PSR and feedback loop dynamics is analyzed to facilitate an informed design procedure for optimized overall PSR. Finally, we implement an output-capacitorless LDO with a buffer stage to verify the analyses in this work. In this design example, the effects of the reduced rdsof the power transistor in an advanced process with very low dropout voltage are discussed and a feed forward ripple cancellation (FFRC) scheme is implemented to further enhance the PSR performance.

This article presents a four-phase adaptive on-time (AOT) controlled buck converter with an ultra-fast load-transient response. A dynamic-frequency clock generator is proposed to generate and auto-synchronize three duty signals with 90°, 180°, and 270° phase shifts based on an already-generated duty signal. Interleaving angles between phases are always kept constant even when the switching frequency varies. Unlike the traditional pulse distribution scheme in constant on-time (COT) multiphase buck converters, the generated pulses no longer need to be sequentially distributed to different phases, but synchronized to one phase instead. Therefore, a much faster load-transient response can be achieved. A transient-enhancement scheme is also proposed to remove the speed limitations introduced by the error amplifier (EA) during load transient. The fast response merits of the AOT controller can thereby be fully taken advantage of while a relatively constant operating frequency is maintained under different input and load conditions. Simulated in a 180-nm BCD process, the proposed converter shows a fast load-transient response with 102-mV output voltage droop and 754-ns settling time for a 6A/1ns rapid load current step, where a 22-μF decoupling capacitor with a relatively large equivalent series resistance (ESR) of 15 mΩ is used. Besides, this work achieves a peak efficiency of 89.7% for 5V-to-1.4V conversion, while the efficiency is maintained at >75% over a wide load range from 1 A to 10 A.

This paper proposes an inductor-first two-inductor two-flying-capacitor (2L2C) multi-path hybrid DC-DC Converter. The proposed converter operates with a switching frequency of 2MHz, an input voltage range of 3 V to 5 V, and an output range between 0.8 V and 1.2 V using only 2-V NMOS power transistors. This hybrid DC-DC topology enables continuous input current and thus alleviates electromagnetic interference (EMI) issues. The two inductors operate in an interleaved manner, reducing the output current ripple. The switched-capacitor network decreases the average inductor current. This work is simulated in a 180-nm BCD process. Both inductors are 470nH with 29-mΩ DCR, while both flying capacitors are 10μF with 10-mΩ ESR. We obtain a peak efficiency of 96.89% at 400 mA load for a 4V-to-1V conversion.

This paper presents a 12V-input 1.8V-0.8V-output multiple-output hybrid buck (MOHB) DC-DC converter with a shared flying-capacitor (CF0) and real-time CF0voltage calibration, while the main control loop uses a pulse-width modulation (PWM) control scheme. With the proposed time-interleaving operation scheme, the MOHB converter has no cross regulation during load transient. The real-time CF0voltage calibration ensures that the voltage across CF0 equals VIN/2. The MOHB converter is designed with four outputs and simulated in an 180nm BCD process. Each output employs a 1μH power inductor with 19mΩ DCR and one 4.7μF flying capacitor. With 12V input, one output equals to 1.8V and other outputs equal to 1V, the peak efficiency 95.2%.

This article presents a capacitorless linear low dropout regulator (LDO) with an N-type pass transistor that features high efficiency, fast transient and good power supply rejection (PSR) suitable for system-on-chip (SoC) integration. This LDO utilizes a pole-tracking compensation scheme and a transconductance-boosted (gm-boosted) folded-cascode EA to achieve high bandwidth. As a result, the LDO achieves a fast transient response and high PSR corner-frequency. Moreover, feedforward ripple cancellation (FFRC) is also incorporated to enhance the PSR performance further. The proposed LDO is fabricated in a 65nm CMOS process. It features PSR performance better than -65dB across the full load range at frequencies lower than 100kHz. And its undershoot and overshoot in response to a 1mA-to-100mA load transient with an edge time of 100ns are 83mV and 10mV, respectively.

Switched-capacitor-inductor dual-path hybrid DC-DC converter can achieve high power density and efficiency, with reduced inductor voltage and current stresses and thus reduced inductor conduction loss and volume. However, it suffers from a large output ripple due to the hard-charging of the switched-capacitor (SC). To take advantage of recent in-substrate or on-chip high-density capacitor technologies, this paper proposes a multiphase interleaving operation for the dual-path SC hybrid converter, increasing the equivalent switching frequency and reducing the amplitude of the current ripple. It achieves a significant output ripple reduction within negligible efficiency degradation. The analysis and simulation results prove that the proposed scheme is a better method for reducing output ripple than increasing operating frequency or reducing power transistor size in the hard-charging path.

This article presents a resonant switched-capacitor (SC) parallel inductor (ReSC-PL) hybrid buck converter with reduced inductor current for high and wide voltage conversion ratio (VCR). The proposed ReSC-PL buck converter lowers down the switching node voltage with${V} _{\text {IN}}$-related flying capacitors and reduces the inductor current${I} _{\text {L}}$with${V} _{\text {OUT}}$-related flying capacitors. Therefore, it can always effectively reduce${I} _{\text {L}}$to a value below$0.5\sim 0.67$of the output current${I} _{\text {O}}$for high VCRs ranging from 10 to 20. In addition, by utilizing the parasitic inductor, this design effectively reduces the glitches on the output and forms a resonant SC operation to further improve the conversion efficiency. This work, fabricated in 180-nm Bipolar-CMOS-DMOS (BCD), occupies an area of 8.88 mm2. Measurement results show that the proposed ReSC-PL buck obtains a peak efficiency of 91.8% and a peak current density of 350 A/cm3 with a power inductor as small as$2.5\times 2\times 1.2$mm3, with 12-V input and 0.6-V to 1.2-V output, and 5-A maximum output current.

Gallium-Nitride (GaN) high electronic mobility transistor (HEMT) enables faster switching frequency for buck converters. Therefore, high dV/dt immunity and small deadtime of the switching node become important indicators for GaN-based buck converter. This paper presents a high switching frequency GaN gate driver with an asymmetrical noise current clamping technique for the floating level shifter for 5000V/ns dV/dt noise immunity in simulation and over 60V/ns immunity in measurement. Meanwhile, the proposed deadtime generator achieves adaptive deadtime control without a down level shifter nor fast comparator for sensing operation state of the buck. The proposed driver was implemented in a$0.18\mu $m BCD process, used in a GaN-based buck converter for verification. It achieves 7.45ns and 1.1ns deadtime for the VSWtrailing and leading edge, respectively. The buck converter obtains 86.5% peak efficiency for 12V-5V conversion, with 10MHz switching frequency.

This article presents a stability analysis method for single-inductor multiple-output ordered power distributive control (OPDC) DC-DC converters. In OPDC converter, both the output voltage and the load current affect the stability, which may eventually cause subharmonic oscillation. The cross-regulation issue of the OPDC control further increases the complexity compared to a single-output converter. This paper derives the stability judgment equation and proposes an optimal output sequencing strategy for stability consideration. Then, a compensation criteria is derived and compared with the traditional single-output current-mode control. In the end, an equivalent compensation scaling factor K is given to evaluate the effects of the output sequence on the required compensation amplitude.

This paper proposes a radio-frequency (RF) cross-connected (CC) rectifier with LC source degeneration (CCLC). The LC network resonates at twice of the working RF frequency, shaping the drain-source and gate-source voltages of the rectifying transistors of the CC rectifier. As a result, the proposed scheme reduces the transistors’ reverse current and the shoot-through current, and thus the root mean square current of the switches, improving the power conversion efficiency (PCE). Meanwhile, it has a better input impedance matching over a wide input power range from the voltage reshaping. Subsequently, we implement the CCLC topology in both one-stage and two-stage CC rectifiers. To reduce the silicon area, we design coupled inductors for the two LC networks of the two-stage CCLC rectifier. We fabricated the rectifiers using a 65-nm CMOS process. The measured PCE of the one-stage and two-stage rectifiers are 67.6% and 61.2%, respectively. The proposed scheme has a wider dynamic range than previous works.

This paper presents a fully-integrated flexible dual-ring switched-capacitor (SC) converter to address the limited output voltage resolution in conventional SC converters. Based on the concept of reconfiguring multiple SC cells in series, the proposed dual-ring SC (DRSC) converter offers various combinations of cascading stages through the outer main ring configuration. Furthermore, the inner sub-ring operation allows for a more flexible selection of output nodes, enabling different power path interconnections and increasing the number of available voltage conversion ratios (VCRs). With 9 fractional VCRs, the converter offers a wide output range and fine output resolution. Compared to traditional SC topologies, the proposed topology exhibits the lowest slow switching limit resistance (R$_{\mathrm {SSL}}$) and the most favorable G-V2 metric, indicating high power efficiency. In addition, to reduce the parasitic capacitance, triple-well junction capacitors with increased reverse bias voltage were proposed. Parasitic capacitance with as low to 0.4% of the main capacitance was achieved. 3.9% efficiency improvement was measured. The chip was fabricated in a 180nm CMOS process and measured with 83% peak efficiency and 200mA maximum load current.

This paper presents a single-inductor multiple-output (SIMO) DC-DC converter with fixed-frequency victim-last charge control. This scheme switches the load-transient channel (victim) to the last of the charging sequence, addressing the inherent cross-regulation issue in conventional charge control SIMO. We first analyze why the conventional fixed-frequency charge control has such an issue. Then, we present the working principle of the proposed scheme. After that, we propose a charge-error calibration technique that minimizes the side effects caused by victim-last control, ensuring a smooth order switching of the original last channel. We implemented and fabricated the proposed SIMO DC-DC converter in a 0.18-$\mu $m BCD process. Measurement results show that we are able to reduce the cross-regulation to 0.057mV/mA with a 225-mA load step under fixed switching frequency. The measured peak efficiency is 84.1%.

This paper presents a fully-integrated reconfigurable dual-ring switched-capacitor (DRSC) converter that overcomes the coarse output voltage resolution limitation of traditional switched-capacitor (SC) converters. The proposed DRSC converter cascades multiple stages of SC cells and achieves a fine voltage conversion ratio resolution from 1/n to (n-1)/n, where n is the number of phases. To improve efficiency, the bottom-plate parasitic loss is mitigated by the charge redistribution technique. Also, the power switches are divided into several segmentation groups to reduce the output ripple with different loads. This work is designed in a 180nm CMOS process with 30 cascaded reconfigurable SC power cells. It achieves a wide output voltage range of 0.5-3.3V from a battery input voltage (2.7-4.2V). The load regulation is implemented with a pulse-frequency modulation (PFM) control. The simulated peak efficiency is 78%, with a load current range of 0 to 20mA, using 1.5nF on-chip capacitors in total.

This paper presents a hybrid single-inductor bipolar triple-output (SIBTO) DC-DC converter for active-matrix organic light-emitting diode (AMOLED) displays. Generating the bipolar rails$V_{\mathrm {OP}}$and$V_{\mathrm {ON}}$for the pixel array and the analog rail AVDD for the source driver with a single inductor greatly reduces the system size and cost. This work adopts the floating negative output topology for an ultra-clean positive output. In addition, we propose a push-pull charge balancer to compensate and regulate the$V_{\mathrm {OP}}$, improving the line and load regulation with continuous currents and acceptable power consumption. This work also proposed a slow-comparator based ordered power distributive control (SC-OPDC) to regulate the AVDD with a pulse-skipping scheme to reduce the power loss. The designed power transistor buffers with adaptive deadtime control improve power conversion efficiency and decrease the required minimum load current of AVDD. The proposed SIBTO converter, implemented in 0.18-$\mu \text{m}$BCD process, operates at 1.67 MHz. It achieves a peak efficiency of 94.1% at 0.88 W output and a maximum output power of 3.67 W with an efficiency of 87%. The maximum output voltage ripples are 5 mV, 17 mV, and 7.5 mV for$V_{\mathrm {OP}}$,$V_{\mathrm {ON}}$, and AVDD, respectively.

Parallel connected low-dropout regulators (LDOs) are commonly used to share the large load current in communication baseband systems. This paper presents a PCB-friendly, reconfigurable master-slave parallel LDO scheme with analog regulation and digital distribution, to deliver Ampere-level load current with small current mismatches. The proposed LDO adopts a series analog-digital merged control, where the first loop is a high-gain analog error amplifier for high-accuracy regulation, and the second loop utilizes a 6-bit successive approximation register (SAR) analog-to-digital converter (ADC) for the tradeoffs between resolution, energy-efficiency, and fast response. Each LDO can be configured into the master or slave mode. When multiple LDOs are connected in parallel, the master LDO also controls the digital power cells in the slave LDOs. By employing an auxiliary constant current control, the power cells in each LDOs work as a constant current source array. The same control code naturally enables the output current balancing among each LDOs. Fabricated in 65-nm CMOS, the proposed LDO obtains an excellent load regulation of < 1.5mV/A across the full load range of 0-1A, with 99.9% peak current efficiency. For four parallel LDOs with each delivering 1-A load current, the measured current-sharing mismatch is only < 0.76% with no additional external components.

High-frequency buck converters need a fast transition of switching nodes (high dv/dt). Such high dv/dt, especially the positive one, can cause malfunction of a conventional pulse-triggered active-coupled (PTAC) level shifter that is used to control the high-side NMOS switch. In this work, we first discuss the dv/dt immunity of conventional PTAC level shifters. Subsequently, we propose a new scheme to block the noise current during the dv/dt sequence, allowing an almost full immunity to the positive dv/dt. With this scheme, the maximum dv/dt is determined by how well the circuitry is protected from the overvoltage during the dv/dt sequence. We design a 20-V buck converter with this level shifter, fabricated in 180-nm BCD process. Experimental results show it works correctly under a 67-V/ns dv/dt.

This paper proposes a hybrid boost converter for $\gt100V$ LED lighting applications. The proposed boost converter uses one flying capacitor to reduce the switch voltage stress, average inductor current, and inductor current ripple, and also to prolong the duty cycle (D) for the same voltage conversion ratio (M). Therefore, the proposed topology has reduced switching, conduction, and core losses, exhibiting also an enhanced step-up capability. Hence, the proposed boost converter considerably improves the power conversion efficiency (PCE), with M=(2–D)/(1–D). Besides, the proposed boost converter automatically sets the voltage on the flying capacitor to VOUT– $\mathrm{V}_{IN}$. Here, we simulate both the conventional and the proposed boost converters in Cadence Spectre with commercial device models. The proposed boost converter improves the peak PCE from 96.8% to 97.4%, with ${V}_{IN}=24V, V_{OUT} =103.5V$, and IOUT=1 A. That is equivalent to 18.75% total loss reduction.

The series-capacitor boost converter (SCBC) requires a duty cycle ($D) \ge0.5$control, otherwise has issues of power switch overstress and inductor currents imbalance. Then, we cannot use the SCBC in wide conversion ratio (CR) applications that requireCR$D \ge0.5$control does not allow$D$to increase smoothly from 0 during start-up, causing severe inrush inductor currents. As a solution, we propose two control schemes on the capacitor-cross-connected (CCC) boost converter, which is the symmetric version of the SCBC. With the proposed hard-charging control, the CCC converter allows$D < 0.5$without overstress or imbalance issues, thus extending theCRrange and facilitating a soft start-up. In addition, we propose a soft-charging control that enhances the efficiency for 3CRCRexpressions under these two types of controls. Finally, we propose a compact centrosymmetric floorplan that reduces the switching nodes’ ringing, verifying the proposed schemes with a 2.8-to-8.4-V input / 24-V output prototype converter. It exhibits a soft start-up with the proposed control. Under an 8-V input voltage and 1.5-A output current, the peak efficiency of the proposed hard-charging and soft-charging control is 94.7% and 96.3%, respectively.

The Hybrid DC-DC converter, especially with multiple inductors targeting high current delivery, has the advantages of high efficiency and power density with a large voltage conversion ratio (VCR), due to the combination of the benefits of both switched-capacitor-based and inductor-based buck converters. However, a higher number of inductors means that the energizing time for each inductor has more limitations, resulting in a relatively narrower VCR range. To reduce the conduction loss and extend the voltage conversion ratio scope, this paper presents a symmetrical double step-down (SDSD) converter with a VCR range up to 1/3, regulating an output voltage interval of 0.5 V-0.8 V from a 2.7 V-4.2 V Lithium-ion battery. This converter, implemented in 65 nm CMOS, occupies a core active area of 1.53 mm2. This work obtains 86.5% peak efficiency and 326 mA/mm2 maximum current density, with an effective switching frequency of 3 MHz.

This paper presents a high-current calibration-free analog-digital hybrid controlled LDO for large-area digital load. The proposed architecture has the advantages of an analog controller (continuous and high DC accuracy) with distributed digital power transistors (flexible and scalable for high current applications). Distinctive from the conventional digital LDOs that directly quantize the output voltage, the proposed LDO utilizes an error amplifier (EA) to pre-amplify the$\text{V}_{\mathrm {OUT}}$error. Then, a 5-bit time-to-digital converter (TDC) quantizes the processed analog error signal subsequently transformed into a thermometer code that directly controls the distributed digital power transistors. This design can pull off high DC accuracy even without calibration. Besides, we implement an auxiliary constant current (ACC) circuit to solve reliability issues and to improve the stability under a large voltage dropout. Fabricated in a 28-nm bulk CMOS process with a 1.2-A load capability, the proposed LDO achieves 2-$\mu \text{V}$/mA load regulation and close to 1.5% output accuracy. By employing a wide bandwidth EA and a fast TDC, the hybrid LDO can obtain a fast transient response. The measured undershoot is 70 mV with a 0.6-A load step within 10-ns edge time, and the output voltage can scale from 0.6 V to 0.9 V within 30 ns.

This paper presents a dual-branch series-parallel hybrid buck converter with flying capacitor voltage auto-balancing and reduced output impedance. The proposed converter automatically and inherently balances the flying capacitor voltages as one-third of the input voltage. Besides, the proposed converter operates in four states per cycle rather than the conventional six states, leading to a feasible Type-III compensation of the analog pulse-width modulation (PWM) controller. Moreover, due to the multiple parallel current paths in the switched-capacitor network, the proposed converter reduces the output impedance, thus decreasing the conduction loss. Finally, validated in 65-nm CMOS, the proposed converter regulates a 0.55 V–1 V output voltage from a 3.6 V input voltage over a large output power of 0.45 W with 82% peak efficiency, and switching frequency up to 5 MHz. It also automatically sets the flying capacitor voltages at 1.2 V.

This paper presents a single-stage tri-path buck converter with reduced inductor current and self-balanced flying capacitor voltage. The proposed converter introduces capacitor paths to reduce the average inductor current and inductor current ripple, hence decreasing the conduction loss. Operating with two states per conversion cycle, it exhibits a relatively low voltage conversion ratio of${D}$/(1$+\,\,2{D}$). Besides, it realizes a self-balanced flying capacitor voltage in the charge redistribution phase. Similar to the conventional buck converter, the proposed converter in continuous-current mode only has two complex poles. Therefore, we design a Type-III compensator to obtain a good transient response. Moreover, the circuit does not require extra supplies for gate drivers due to the reutilization of the flying capacitor voltages, eliminating additional circuit and power overheads. The proposed converter, validated in a 65-nm standard CMOS technology, regulates a 0.7 V – 1 V output voltage from a 3.3 V – 4 V input voltage, delivering a maximum output power of 270 mW. The peak efficiency is 84%, with a switching frequency up to 5 MHz.

Since the power consumption of data centers keeps increasing, a 48-V rack power distribution system replaces the conventional 12-V power bus to reduce the power delivery IR losses. Meanwhile, the 48 V needs conversion into 1 V or lower at the point-of-load for microprocessors. A 48V-to-12V DC-DC converter can serve as a first stage between the huge gap of 48V-to-1V, in a two-stage voltage regulator module (VRM). Thus, this paper presents a 3-phase resonant switched-capacitor ( 3Φ-ReSC) converter as the first stage of the VRM. Different from the reported solutions, 3-phase resonant operation reduces the current stress across each small-size GaN switch, and thus improves the power conversion efficiency. In addition, we also present the theoretical analysis and design procedures for the 3Φ-ReSC converter. We demonstrated the proposed 3Φ-ReSC converter with a 98% peak power efficiency at an output current of about 1 A, with a maximum output current of 10 A.

A 0.6-V 100-mA fully-integrated digital low-dropout regulator (DLDO) with adaptive current step size control is presented in this paper. By dividing the main power PMOSs into ten blocks with different unit-cell sizes, the proposed DLDO can turn-on/-off small power PMOSs in light load and large ones in heavy load conditions. High regulation accuracy in a wide load range and fast transient response are hence achieved. In addition, an auxiliary power MOS block, which consists of both PMOS and NMOS transistors, is adopted to eliminate the limit cycle oscillation (LCO) in light load condition and to further accelerate the response speed. The proposed DLDO is fabricated in a 65-nm low-power CMOS technology with an active area of 0.17 mm2including an on-chip output capacitor of 1nF. The measured undershoot and overshoot voltages are only 53 mV and 37 mV, respectively, when the load current changes between 0 and 100 mA. The quiescent current is 34.6 μα, while the maximum current efficiency is 99.96%.

A fully integrated single-input dual-output switched-capacitor converter with dynamic power-cell allocation for application processors is presented in this summary. The power cells can be dynamically allocated according to the loads, and the efficiency is improved by 4.8%. A dual-path voltage-control oscillator (VCO) that works independently of the power-cell allocation is proposed to achieve a fast and stable regulation loop. The converter achieved peak efficiency of 83.3% and maximum combined load-currents of 100mA while maintaining minimized cross regulation.

A switched-capacitor DC-DC converter with a low output voltage ripple and high efficiency is presented in this summary. To achieve a wide input and output voltage range, a 3-clock-phase operation is proposed to achieve 6 voltage conversion ratios (VCRs) with only two discrete flying capacitors. A digital ripple reduction scheme is utilized to achieve up to four times reduction in output voltage ripple. The digital design also improves the design flexibility. The converter can deliver a 250mW maximum power to a wide output range of 0.5 V to 3 V with an input range of 1.6 V to 3.3 V, and achieves a peak efficiency of 91%.

This paper presents a dual-loop digital low-dropout regulator (DLDO) with asynchronous-flash (AF) binary coarse tuning for fast transient response. In steady state, the DLDO operates with a unary-weighted low power fine-tune loop to improve the regulation accuracy. Besides, a freeze mode is also employed to further reduce the power budget and to eliminate the limit cycle oscillation phenomenon. When a load-transient is detected, the proposed AF bidirectional shift register will direct the binary-weighted power switches for coarse and fast tuning. The prototype is fabricated in a 28nm bulk CMOS process. With VIN=0.5V and 50mV dropout, the AF-DLDO can deliver 33mA output current and consume only 10.5μA quiescent current. We measured 102mV voltage undershoot for a 30mA/20ns load step, showing a 0.11ps FOM.

This paper presents a single-stage wireless charger using a current-mode active rectifier with accurate output current regulation for efficient wireless charging. As we know, the rectifier processes an AC input voltage/current and a pulsing output current which are difficult to be accurately sensed on chip with small area and power overheads. The proposed current sensing technique uses a replica sensing stage in parallel with the main power stage. It consists of two small cross-connected sensing PMOS transistors, a small filtering capacitor, and a dynamic replica load. In addition, by adaptively tuning the delay of the power NMOS driving signal, the charging current is regulated precisely. This single-stage wireless charger operates at 6.78MHz, and is designed in a 0.35μm CMOS process. Simulation results show a minimum 97.5% current regulation accuracy over a 10× (from 100mA to 1A) output-current range. The peak efficiency of 94% is achieved with 4.2W output power.

To treat retinal degenerative diseases, a transcorneal electrical stimulation-based system is proposed which consists of an in vivo eye implant and an in vitro control device. The eye implant is wirelessly powered and controlled by the in vitro device to generate the required bi-phase current pattern for the transcorneal stimulation with an amplitude range of 5μA~320μA, a frequency range of 10Hz~160Hz and a duty ratio range of 2.5%~20%. Only one pair of coils is used for both the power link and the bi-directional data link. Except the secondary coil, the eye implant is fully integrated on chip and fabricated using UMC 0.13μm CMOS process with a size of 1.5mm by 1.5mm. The secondary coil is tiny and fabricated on a PCB with an outer diameter of only 4.4mm. After packaging with biocompatible silicone, the whole implant has a dimension of 6mm diameter with a thickness of less than 1mm. The whole device can be put on the sclera and beneath the eye's conjunctiva. Measurement results verify the system's functionality and demonstrate the performance.

Charge balance law based on conservation of charge is stated and employed to analyze charge pumps. For micro-power on-chip implementations, both the positive-plate and the negative-plate parasitic capacitors have to be considered. A first iteration approximation analysis is proposed to analyze charge pumps with parasitic capacitors. Using a 0.35µm CMOS process, 8X linear, Fibonacci and exponential charge pumps are designed and their performances are compared and confirmed by simulations.