The CMUT devices presented in this paper were fabricated using a commercially available MEMSCAPs PolyMUMPs process. The moveable membrane evolves from the available single layer polysilicon. COMSOL simulations were used to model and investigate the effects of a 140 μm and 105 μm radius membranes that are 1.5 μm and 2 μm thick respectively. The results for two different structures designed to operate below 350 kHz are demonstrated in this work. Simulations show that both the devices presented show displacement of over 40 nm. The device snap shut was observed beyond 40 V. This frequency range is suitable to have high SNR and accurate distance measurements. Reducing the size of CMUT devices for the proposed frequency range was a challenge, sorted in this paper. A device capable to generate ultrasound close to 50 kHZ is also presented.

Starting with a brief review on 0.1-/spl mu/m (100 nm) CMOS status, this paper addresses the key challenges in further scaling of CMOS technology into the nanometer (sub-100 nm) regime in light of fundamental physical effects and practical considerations. Among the issues discussed are: lithography, power supply and threshold voltage, short-channel effect, gate oxide, high-field effects, dopant number fluctuations and interconnect delays. The last part of the paper discusses several alternative or unconventional device structures, including silicon-on-insulator (SOI), SiGe MOSFET's, low-temperature CMOS, and double-gate MOSFET's, which may lead to the outermost limits of silicon scaling.