This work investigates proposed maximum-powerpoint tracking (MPPT) approaches for a fully integrated hybrid voltage converter (H-VC) intended for alternative energy sources in low-power Internet of Things (IoT) systems, where passive components and power supply rail stability impose severe constraints. A monolithic Hybrid-Dual-Path (HDPC) voltage converter with an on-chip$L_{\text{DC}}=15.07 n H$inductor and strongly limited total capacitance ($C_{\text{IN}}=C_{\text{OUT}} \approx 2.5 n F$) is considered, with 1.5 V output voltage regulation provided by a continuously operating shunt-type regulator. The two MPPT concepts are analyzed: (i) iMPPT based on the fractional open-circuit-voltage (FOCV) principle, which is energy-efficient but requires periodic$V_{\text{IN,OC}}$sampling via short-time disconnection of alternative energy sources (AES), and (ii) oMPPT, which maximizes extracted load power by optimizing the combined product$\eta_{\text{MPPT}}.\eta_{\text{VC}}$and provides instantaneous power observability in a form of digital code. The feasibility and performance are evaluated in Cadence using a TSMC 65 nm CMOS technology and a realistic PV model (KXOB25-14X1F), across irradiance levels of 5-500 W/m2corresponding to PIN,MPPfrom$114 \mu W$to 14.8 mW. Simulation results show that both approaches regulate operation over a wide switching-frequency span of roughly 0.9-62 MHz via FrequencyShift Modulation Control (FSM-C). Overall, iMPPT is favored when minimal control overhead is paramount, whereas oMPPT offers superior scalability and algorithmic flexibility for broader AES applicability at the cost of up to 5.5 times higher power consumption.

This work presents the 1.2 V Low-Dropout Regulator (LDO) designed in a standard 65 nm CMOS technology using data obtained from experimental verification of 9 prototype chips. The measurement of standard parameters that were evaluated included Load Regulation (LDR) in the output current I out range from$\mathbf{1} \boldsymbol{\mu} \mathbf{A}$to$\mathbf{3 0 0} \boldsymbol{\mu} \mathbf{A}$, Line Regulation (LNR) at$\boldsymbol{I}_{\text {out }}$of$100 \mu ~\mathrm{A}$and$300 \mu ~\mathrm{A}$, Drop-Out voltage and PSRR parameter. In addition, the presented LDO dispose of a Slew-Rate Enhancement function, which can be activated externally. In all cases of this feature activation, the measurement proved its expected and correct function with reducing the settling time value and, depending on the direction of the output current change, also the voltage value for overshoot or undershoot.

This paper presents the design and measurement results of tunable Relaxation Oscillator ($\mathbf{R x O}$) proposed in standard 65 nm CMOS technology. The proposed RxO achieves the wide oscillation frequency range with fine tunability and low power consumption. The achieved results were obtained by measuring the prototype chip and show that the proposed oscillator can be tuned within the range of 72 kHz to 123 MHz, with a tuning step below 0.77 % for digital tuning and$0.53 \% / \text{mV}$for analog tuning with respect to the absolute value of the oscillation frequency. The low power consumption from$1 \text{nW} / \text{kHz}$to$23 \text{nW} / \text{kHz}$was observed. The figure of merit of 64 dB has been found to demonstrate an excellent dynamic range with fine tunability features.

This paper presents tunable voltage reference (TVR) designed in a standard general purpose 65nm CMOS technology. Designed circuit is based on two-transistor (2T) voltage reference (VR) with digitally controlled operational amplifier (OPAMP). Developed TVR provides stable output voltage from 0.38 V to 1.1 V with non-linear tuning step under 0.5% of the output voltage (from 1.9 mV to 2.9 mV). The supply voltage in the range from 0.91 V to 1.5 V is used. The circuit offers parameter PSRR = -53.59 dB (at 1 kHz) and line regulation (LNR) of 0.35% in the worst case. The required area is 0.0185 mm2. The proposed TVR was used to precise frequency tuning of oscillator. Provided results are obtained from both simulations and measurement of the manufactured ASIC prototype.

This paper presents indirect Maximum Power Point Tracking (MPPT) method for solar-powered energy harvester. MPPT is based on Constant Voltage algorithm with enhancement in form of adaptive tuning step. Fully integrated digital control circuit is part of Pulse Frequency Modulation (PFM) control that ensures the maximum energy extraction from the solar cell by adjusting switching frequency of Voltage Converter (VC). Fully on-chip inductor-based step-up converter provides regulated output voltage$\mathrm{V}_{\text{out}}=1.5\mathrm{V}$under different irradiance conditions. The developed system manufactured in a standard 65 nm CMOS technology is self-powered using two solar cells. The energy harvester can be used as a power supply for energy-autonomous electronic devices or low-power applications.

This work presents a dedicated method of analog integrated circuit (IC) autocalibration, which was used to calibrate a voltage reference with the output voltage value of 96 mV . The reference accuracy might be significantly influenced by fluctuations in the manufacturing process. The essence of this technique is to suppress this undesired influence of process variations in terms of the corner conditions of 130 nm CMOS technology. All analog parts of the proposed autocalibration system are presented at the transistor level. The output of the calibration subcircuit is a digital signal controlling the autocalibration.

In this paper, methods suitable for sensing the output load current (or current consumption) of analog circuits were studied and analyzed. The main focus was paid on approaches that can be implemented on a chip. The proposed approach for sensing the output current of a DC-DC converter is based on measuring the slope of a voltage sensed by an output bypass capacitor. Such an indirect sensing approach shows better efficiency than a common shunt resistor sensing method. The presented approach was used in a flyback type DC-DC converter. The simulated results prove better voltage conversion efficiency using the proposed indirect measurement approach.

This paper presents a novel on-chip digital method of calibration for a fully differential difference amplifier (FDDA), which is aimed at improved performance and reliability through enhanced robustness against variations of process parameters, voltage, temperature, and ageing drift. The proposed method was designed and verified within 130 nm CMOS technology design kit in Cadence environment. Calibration hardware is built-in with the calibrated FDDA, and the whole integrated system is able to operate with only 0.4 V power supply. The effectiveness of the proposed calibration method was examined mainly by evaluation of the FDDA input offset voltage using Monte Carlo, process corners and ageing analyses performed for the temperature range from -20° C to 85° C. The work established metrics for comparison of different calibration methods (i.e. digital calibration, chopper stabilization, analog calibration and autozero), which significantly differ in fundamentals of their operation. The proposed digital calibration outperforms its alternatives, while the precision of calibration, area and power consumption overhead are considered. The less advanced topology of digital calibration was previously implemented for variable-gain amplifier with considerable success (residual offset of the calibrated amplifier reaches fair levels of 13 μV to 167 μV). The concept proposed in this work utilizes advanced high precision calibration algorithm.

The paper addresses a development and evaluation of well-known EKV MOS transistor model with focus on the ultra low-voltage / ultra low-power analog IC design employing rather “exotic” bulk-driven technique. The presented contribution can be viewed as an extension of already established compact simulation model with modifications to the original parameter extraction flow. The article contains a brief description of EKV model fundamentals, a novel parameter extraction flow and most importantly, the comparison of developed EKV model with the foundry-provided BSIM model (v3.3) and the experimental measurement data obtained from prototype chip samples fabricated in 130 nm CMOS technology.

The paper addresses an evaluation of dynamic properties of silicon-proven ultra low-voltage/low-power rail-to-rail comparator fabricated in general purpose 130 nm CMOS technology. The experimental results confirm a correct operation at power supply voltage of VDD= 0.4 V and good agreement with post-layout simulation results can be observed. The proposed comparator topology has been proven to work in nW range and is also capable of operation with even lower power supply voltages and without a need of post-processing trimming. The article contains incremental results of performance analysis of discussed circuitry already published in [1].

This paper presents a novel hardware architecture of dynamic memory manager providing memory allocation and deallocation operations. Due to very low and constant latency of these operations with respect to the actual number and location of free blocks of memory, the proposed solution is suitable for hard real-time and mixed-criticality systems. The proposed hardware-accelerated memory manager implements Worst-Fit algorithm for selection of a suitable free block of memory that can be used by the external environment, e.g. CPU or any custom hardware. The proposed solution uses hardware-accelerated max queue, which is a data structure that continuously provides the largest free memory block in two clock cycles regardless of the actual number or constellation of available free blocks. The proposed memory manager was verified using simplified version of UVM and applying billions of randomly generated instructions as test inputs. A synthesis into Intel FPGA Cyclone V was performed, and the synthesis results are presented as well. The memory manager was also synthesized into 28 nm technology with 1 GHz clock frequency and the power supply voltage of 0.9 V. The ASIC synthesis results show that the proposed memory manager consumes additional chip area from 35% to 70% of the managed memory.

This paper deals with cross-implementation of analytical and physical fundamentals of ultra low-voltage charge pumps. The analysis is based on precise, general formulas including characteristic parasitic effects valid for linear charge pumps. The parasitic effects are extended by non-linear parasitic capacitances represented as equivalent linear model of a switched transistor itself. The discussion about non-linear and linear behaviour of these parasitics is also included and demonstrated using cross-coupled, dynamic threshold implementation, where the EKV model of transistors has been utilized. The paper also introduced a new design rule for design of charge pumps based on transistors working in sub-threshold region to maximize the power throughput. This is achieved by tuning the operation conditions to the boundary case.

The paper addresses a novel topology of ultra low-voltage comparator with rail-to-rail input voltage range and selectable level of hysteresis designed in a standard twin-well 130 nm CMOS technology. The nominal power supply voltage of 0.4 V was used, and the working temperature range was set to the industrial standard from -20 °C to 85 °C. The proposed comparator design is intended to work in an energy harvesting system. Hence, low power consumption is the key requirement. The comparator employs bulk-driven transistors in the input stage and operates in so-called current mode. The designed comparator circuit draws less than 5 μA in typical conditions but its function and robustness have been verified across all possible process and temperature corners. The design was submitted to foundry for manufacturing and the measured data can be expected soon.

With the emergence of always-on wireless sensing nodes, AC/DC power conversion solutions for sub 1 W applications are required. Existing approaches are not efficient for such output loads, and therefore, new solutions need to be provided. In this paper, we propose a solution that is optimized for operation with output loads up to 500 mW, while high efficiency and close to zero no-load consumption have been our foremost design goals. The proposed design is implemented in a high-voltage CMOS process and transistor level simulation results show improved properties of the proposed solution over the existing ones.

The paper is a contribution to the 50th anniversary celebration of the International Test Conference (ITC) and its Global Test Forum (GTF), which honors the geographic breadth of the test community and highlights the global reach of ITC during the past 50 years. It covers the past, present, and future of the International Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS), a symposium which belongs to prominent test technology related events initiated and supported by the ITC.

In this paper, a two-stage variable gain amplifier (VGA) based on bulk-driven approach is presented. The proposed VGA was designed using the bulk-driven technique, which brings a possibility to operate with ultra-low power supply voltage. In order to achieve rail-to-rail input voltage range, bulk driven input transistors are used. The proposed VGA was designed and implemented in 130 nm CMOS technology. Achieved results, which are obtained by simulation and experimental measurement of prototype chips indicate that the proposed VGA can be useful applied in low-voltage and low-power systems.

This paper presents an efficient hardware architecture of min/max queue, which is suitable for real-time systems due to the constant response time of the queue. This architecture, called Heap Queue, can sort items according to their sorting values and can remove the first item from the queue. The instructions of the Heap Queue architecture have throughput of one instruction per two clock cycles regardless of the actual number of items in the system and regardless of the queue capacity. The developed queue was implemented in FPGA. Achieved synthesis results are presented and compared to the synthesis results of the Rocket Queue architecture. Advantages and disadvantages of the proposed Heap Queue architecture in comparison to the Rocket Queue architecture are discussed.

This paper addresses a design and performance evaluation of ultra low-voltage non-clocked voltage comparator. The circuit was designed in a standard twin-well 130 nm CMOS technology and is intended to work in temperature range of -20 – 85 °C with the power supply voltage of 0.6 V. The proposed comparator can handle the input voltage within the rail-to-rail range. Low-voltage design approaches, namely, g m /I D design methodology in combination with the bulk-driven operation approach have been employed. The measurements on fabricated prototype chips included evaluation of both static as well as dynamic parameters. An excellent correlation between simulations and the measured bench data was observed. The proposed comparator is currently being reviewed and re-designed for even lower power supply voltage of 0.4 V.

This paper deals with the design of a RF rectifier usable for inductively powering implantable medical devices, more specifically a fully integrated on–chip device. This application has specific challenges that need to be met, mainly the weak coupling between the transmitter and receiver, which results in small input power for the rectifier. The use of an on–chip receiver coil puts restrictions on the operating frequency, which is set to 200 MHz. The input voltage is also rather low due to the low quality of on–chip circuit components. The proposed rectifier uses the differential drive cross-coupled bridge topology. A body biasing technique and triple-well NMOS transistors are used to achieve better performance at the low input voltage without the need for additional circuitry. The rectifier was designed in a 130 nm CMOS technology. Effects of the input voltage, power and load resistance on the power conversion efficiency and the output power were investigated. A significant increase in the output power was observed.

This paper presents an efficient hardware architecture of priority queue, which is suitable for real-time systems due to the constant response time of the queue. The proposed architecture is based on shift registers, systolic arrays, heapsort algorithm, the Rocket Queue architecture and dual-port RAMs. This architecture, called Heap Queue, can sort items according to their sorting values and can remove the first item from the queue. The implementation of the Heap Queue architecture has throughput of one instruction per two clock cycles regardless of the actual number of items in the system and regardless of the queue capacity. The developed queue is optimized for low chip area costs, which leads to lower energy consumption too. The Heap Queue architecture has constant time complexity due to two clock-cycle response time of the instructions and therefore, the architecture is highly deterministic. The usage of the queue is recommended for applications in hard real-time systems. The architecture was verified using simplified version of UVM and applying millions of randomly generated instructions. Achieved ASIC and FPGA synthesis results are presented and compared to the synthesis results of the Systolic Array and Rocket Queue architectures. More than 86% of chip area and 92% of power consumption can be saved if Heap Queue is adopted. Advantages and disadvantages of the proposed architecture in comparison to the existing architectures are discussed.

This paper presents the design of a coprocessor that performs data sorting for min/max queues in real-time systems. The proposed architecture is based on shift registers, systolic arrays and heapsort algorithm. Such an architecture, called Rocket Queue, is able not only to sort items according to their sort values, but it is also possible to remove any item from the structure according to its unique ID, which is important for many various applications. Instructions of the Rocket Queue architecture are performed in two clock cycles regardless of the number of items in the system and regardless the queue capacity. The developed coprocessor is optimized for low chip area costs, which leads to lower energy consumption too. The Rocket Queue architecture has constant time complexity, constant critical path length and it is highly predictable, thus also suitable for real-time applications. The architecture was verified using simplified version of UVM and applying millions of instructions with randomly generated sort values. Achieved synthesis results are presented and discussed. These results are significantly better than the results of systolic arrays. More than 41% of logic resources can be saved using the Rocket Queue architecture.

This paper presents design of the inverter-based driver for low-voltage applications, with topology for boosting the transistors overdrive voltage. The proposed driver topology was designed through detailed circuit analysis and optimization, and it is suitable for use in a switched capacitor charge pump. The driver was designed in 130 nm CMOS technology and verified by simulations including technology corners. Core of the proposed driver - the inverter uses power supply voltage of 200 mV. The whole boosted driver achieves a propagation delay of 9.2 ns and energy consumption of 92.12 μW for the value of load capacitor is 100 pF. Due to the low-power consumption, the proposed driver was satisfactory used in a self-powered charge pump systems.

In this paper, a variable gain amplifier designed in 130 nm CMOS technology is presented. The proposed amplifier is based on the bulk-driven approach, which brings a possibility to operate with low supply voltage (i.e. 0.6 V). Since the supply voltage of only 0.6 V is used for the amplifier to operate, there is no latchup risk that usually represents the main drawback of the bulk-driven approach. As an input stage, bulk driven transistors are used, which makes possible to operate in the rail-to-rail input voltage range. Achieved simulation results indicate that gain of the proposed VGA can be varied in a wide range, which together with the low supply voltage feature make the proposed amplifier useful for low-voltage and low-power applications.

An alternative method of fault simulation is presented in this paper. The proposed method is based on impedance calculations in the circuit under test. Calculation time and other properties of the method are addressed and evaluated. Possible application and results evaluation are demonstrated on an experimental circuit. This method could improve the test development time and quality.

In this paper, different topologies of gate-driven and bulk-driven current mirrors designed in 90 nm CMOS technology are presented. Since the conventional MOS transistors can work as a bulk-driven device, there is no need for any modification of the existing MOSFET structure or technology process. The bulk-driven current mirror is capable of operating at power supplies down to the threshold voltage of a standard MOS device. Bulk-driven current mirror topologies were compared to their gate-driven equivalents in terms of main properties and output characteristics. The achieved results prove that the bulk-driven design technique is very promising towards ultra low-voltage analog ICs.

Design of variable-gain amplifier (VGA), based on fully differential operational amplifier is presented. The proposed VGA topology was verified through simulations and analysis of main circuit parameters. The VGA is designed in 0.35 μm CMOS technology using Cadence environment and BSIM3 family of models. Designed circuit works with the power supply of 3.3 V. The simulation results show that gain bandwidth (GBW) of about 12 MHz (for capacitive load of 1 pF) and the total harmonic distortion of less than 1% for input amplitude 100 mV were achieved. Implemented feedback circuit is stable according to phase margin of 68.15°.

This paper presents the design of an improved coprocessor that performs conflict-free task scheduling for dual-core real-time systems. The solution proposed in this paper is based on two algorithms: Earliest Deadline First (EDF) algorithm that is proved to always find an optimal ordering of hard real-time tasks and the priority-based FCFS algorithm that is suitable for non-real-time tasks. The proposed coprocessor can efficiently handle any combination of both types of tasks even though they use different parameters for scheduling. Thanks to HW implementation of the scheduler, the operations are performed in one clock cycle regardless of the current and the maximum number of tasks in the system. The proposed coprocessor is optimized for dual-core CPUs, which can lead to higher performance of real-time embedded systems. Two different approaches for dual-core systems are proposed: semaphore approach and simultaneous processing approach. The simultaneous approach allows the coprocessor to accept and perform both instructions of both CPU cores simultaneously without any conflicts. Both approaches were verified using simplified version of UVM and applying 128 million instructions with randomly generated deadline values. Chip area costs are reduced by up to 35% by performing time precision optimization. The total power consumption is theoretically reduced by up to 50% during the time when the coprocessor is not used by any CPU because the dynamic power consumption is reduced dramatically.

In this paper, a fully differential difference amplifier designed in 0.35 μm CMOS technology is presented. The proposed amplifier reaches high dynamic range and low input noise. Comparison of noise performance of the proposed fully differential difference amplifier to an ordinary differential amplifier has been performed. Simulation results prove that the developed amplifier circuit can be advantageously used in applications that require a fully differential signal. In our work, the proposed amplifier has been experimentally employed in the analog front end of the readout interface for a MEMS (Micro-Electro-Mechanical-Systems) capacitive microphone.

This paper addresses a development of electronic circuits designed for executing fundamental Boolean logic functions based on In AlN/GaN heterostructures. The top-down design flow of the mentioned circuits using an in-house fabrication process is described. The front-end design includes the creation of a scalable behavioral model of stand-alone high electron mobility transistors (HEMTs), followed by the design of basic logic cells and circuits. The back-end flow consists of the full-custom design of lithographic masks required for a successful fabrication process. The paper discusses advantages, drawbacks and challenges of the presented procedure as well as expected electrical parameters of the fabricated circuits.

A novel resistance calculation method based on eigen calculus of the circuit's nodal admittance matrix is described and evaluated in this paper. More specifically, the calculation time efficiency of the method is examined and comparison to the traditional LU factorization based method is made. This evaluation is based on real and complex matrices that are both symmetrical and non-symmetrical as well. Circuits sizes taken into account range from 25 to 3600 nodes. The obtained results demonstrate the time efficiency of this method, especially, for non-symmetrical matrices. The proposed method could be used to speed-up the fault simulations and improve test development of analog circuits.

The paper deals with a new approach to selection of the optimum value of the oscillation frequency towards increasing the efficiency of the oscillation-based test methods in covering hard-detectable short faults in nanoscale technologies. For this purpose, the Describing-Function analysis was used to calculate of the oscillation frequency of a simple oscillator (an analog circuit under test) modeled in MATLAB. Accuracy of the model was evaluated through comparison of computed parameters to parameters achieved for the same circuit in Cadence.

This paper presents the design of a new architecture of digital neurons for use in the feed-forward neural networks (FFNN) and their subsequent implementation on a chip. The proposed neuron uses a special type of multiplication realized by AND gate. Comparison of usual ways of implementing digital feed-forward neural networks using fixed/floating point numbers to the novel architecture using the special multiplication was performed. Consequently, the investigated FFNN architectures were implemented into FPGA and ASIC, where the chip area was the main concern. Chip area and other features of both the new neural network architecture and standard NN architectures we compared and evaluated.

Research presented in this paper is aimed at the comparison of the Oscillation-based Built-In Self Test (OBIST) efficiency in covering catastrophic and parametric faults in active analog integrated filters designed in two different technologies. Sallen-Key topologies of low-pass and high-pass filters were used as Circuit Under Test (CUT), designed in 0.35μm and 90nm CMOS technologies. The presented oscillation test strategy uses the on-chip Schmitt oscillator as the reference frequency source to compensate the influence of process parameter variations. Achieved results show that the proposed BIST approach is fully implementable in nanoscale technologies. Finally, dependence of the fault coverage on the oscillation frequency value was investigated.

This paper presents a numerical approach to DC fault analysis of analog circuits that improves the total computational time and reduces the total complexity of such analysis. The reduction is achieved by utilization of calculus that can substitute conventional simulations and thus, significantly reducing computational time. A detailed description of the approach including its mathematical background is presented. Accuracy and time efficiency are demonstrated on a test circuit.

This paper deals with comparison of two discrete methods for digital trimming of the input offset voltage in operation amplifiers designed in 90nm CMOS technology. Two different topologies based on the binary weighed ladder, one using successive approximation register (SAR) and the other employing a simple counter, were compared. Furthermore, a correction circuit was proposed and used to form the mean offset voltage and increase the probability that its value after trimming process will be near zero. Finally, achieved results and improvements are discussed.

This paper deals with the comparison of the fault coverage of catastrophic faults in active analog integrated filter obtained by the measurement of filter parameters and by the Oscillation-based Built-In Self Test (OBIST) approach. In our experiment, firstly, the cut-off frequency, ripple in the pass band, DC gain in pass band and group delay of the filters have been monitored in the operating mode. Then, during the test mode (OBIST), the filter is transformed to an oscillator, and the oscillation frequency is compared to the frequency from a dedicated on-chip reference oscillator to compensate undesired influence of technology variations. The obtained results on the efficiency of both approaches are compared.

Dynamic supply current test method (IDDTtest) in static random access memory (SRAM) cell arrays is addressed in order to unveil weak open defects. Simulations were carried out on a 64-bit SRAM circuit, where several parameters of the IDDTwaveform were monitored. The SRAM circuit was designed in a 90 nm CMOS technology. Efficiency of IDDTtest in unveiling open defects was evaluated and the achieved results were compared for four SRAM arrays with cells of different cell ratio (CR). Moreover, a solution for transformation of the dynamic current to voltage is presented. After the transformation of the current waveform to a voltage waveform, the parameters of the voltage waveform similar to those of the current waveform are easily monitored and evaluated.

This paper addresses a novel methodology of detecting the completion of computation process of the combinatorial block in asynchronous systems. Logic gates fabricated in CMOS technology draw electrical current in several orders of magnitude higher during the signal transitions than in the idle state. This fact can be used to separate the idle state and the computing activity. The paper presents the fundamental background of the completion methodology, detailed explanation of the sensing circuitry operation, achieved simulation results as well as the comparison to state-of-the-art methods of completion detection.

A new strategy for on-chip test of an operational amplifier as a part of complex analog and mixed-signal systems is described. During test mode, the operational amplifier is disconnected from the rest of the circuit and transformed to an oscillator. To evaluate the circuit, its oscillation frequency is then compared to a frequency given by a Schmitt trigger oscillator, used as the on-chip reference to compensate technology variations. This method might bring a possibility to implement the Oscillation-based Built-In Self-Test (OBIST) for operational amplifiers as a part of complex systems.

The paper deals with dynamic supply current (iddt) test method, where several parameters of the iddt waveform have been monitored. Simulations were performed on two 64-bit SRAM circuits, in which resistive open defects were investigated. The technologies used were 0.35 µm and 90 nm CMOS. The efficiency of iddt test in covering open defects for both technologies was evaluated.

This paper addresses an alternative approach in detecting completion of computation in asynchronous circuits. The proposed method is based on sensing the amount of consumed power supply current. It represents a simple but reliable and effective way of detecting the computation completion in this type of digital systems. The paper presents a novel topology of current sensing circuitry, explanation of the operation as well as simulation results and finally the conclusion.

This contribution deals with the novel conception of design approach to RF wideband and multiband receivers. New methodology of spatial sampling and spatial sampling method of standing wave is presented. Front-end RFIC receiver, utilizing spatial sampling method of standing wave for down converting to baseband and demodulation, has been proposed and analyzed. The whole system is proposed to be implemented in CMOS AMS 0.35mm technology with 2.7 V supply voltage. It works in two bands (in 2 Ghz and 5 GHz ranges). Furthermore, basic building blocks of the RF receiver, such as voltage controlled oscillator, low noise amplifier, spatial sapling unit, additive devices and power detectors have been designed and optimized.

Current Sensing Completion Detection (CSCD) method in asynchronous circuits is addressed. Current Sensing represents a simple but effective and reliable approach to detect completion of computation in asynchronous (self-timed) systems. However, in recent deep sub-micron technologies, several challenges, such as significant influence of process variations, leakage current power dissipation with circuit in off-state, etc., have to be faced. This paper presents an overview of these undesired effects and proposes some prospective solutions.

An experiment comparing the efficiency of different test strategies on a moderate complexity mixed-signal circuit with 1300 nodes is presented. Selected test strategies from the groups of functional, structural and parametric approaches were considered. Bridging faults are taken into account and fault simulations results are shown, where fault coverage, efficiency and quality of the tests are evaluated.

Power devices current sensors based on magnetic force of is presented. The proposed sensors are aimed to be used for switched current testing in power devices with high switched currents above amperes. The advantage of the proposed monitors is in elimination of the undesired voltage reduction and compatibility with the power device control electronics. Description of horizontal and novel vertical magnetic sensors architectures, designs and physical implementations on chip are presented. Several sensor versions were designed in 1.0 µm BiCMOS technology.

An efficient defect-oriented parametric test method for analog & mixed-signal integrated circuits based on neural network classification of a selected circuit's parameter using wavelet decomposition preprocessing is proposed in this paper. The neural network has been used for detecting catastrophic defects in two experimental analog & mixed-signal CMOS circuits by sensing the abnormalities in selected parameters, observed under defective conditions and by their consequent classification into a proper category. To reduce complexity of the neural network, wavelet decomposition is used to perform preprocessing of the analyzed parameter. Moreover, we show that wavelet analysis brings significant enhancement in the correct classification, and makes the neural network-based test method extremely efficient & versatile for detecting hard-detectable catastrophic defects in analog & mixed-signal circuits.

In this paper, on-chip test circuitry performing the transient supply current measurement is presented. The introduced principle makes uses of the parasitic resistance of the supply connection to sense the dynamic supply current. Thus, the monitor does not cause any additional power supply voltage degradation and provides detection capabilities for open defects that usually cause a significant reduction of the I/sub DDT/ current. The proposed monitor does not affect the performance of the CUT and can be efficiently used to test low-voltage CMOS circuits. Significant results summarising possibilities and limitations of the circuit are discussed as well. The design has been implemented together with an experimental CMOS circuit using Alcatel-Mietec 0.7 /spl mu/m CMOS technology and its processing is in progress. Evaluation results of the prototype test chips are presented.