This article presents RF integrated receiver consists of high-gain broadband low noise amplifier (LNA) with balun, Gm-C band-pass filter, and ultra-wideband (UWB) antenna with band-notch design. The proposed wireless integrated CMOS design and analysis are chosen as the receiver of RF circuits to enhance conversion gain low noise amplifier while maintaining high-flatness at broadband. The integrated circuit is fabricated in tsmc$0.18-\mu \mathrm{m}$process. From 3 to 6 GHz, the measured results exhibit high-gain of 16.2 to 17.4dB, noise figure of 4.0dB to 4.4dB with Input-referred third-order intercept point (IIP3) of −20.2 dBm while consuming 14 mA from a 1.8V supply. The measured results exhibit high-gain of 11.7 dB to 13.7 dB, noise figure of 4.6 dB to 4.9 dB with Input-referred third-order intercept point (IIP3) of −20.9 dBm while consuming 6 mA from a 1.0V supply, respectively.

In the drug discovery process, the biological activity value (BAV) of G Protein-Coupled Receptors (GPCRs) targeting ligands is a large consideration. Past BAV prediction on CPU consumes tremendous time and power, yet there is rarely any related acceleration research. Therefore, this paper proposes a series of heterogeneous FPGA-based accelerators for well-performing algorithms to predict GPCRs ligands BAV. Communication delay is reduced by compressing the sparse matrix and directly coupling accelerators on the system BUS. Computation is accelerated by the remapping during the weight storage. Experimental results show that our FPGA accelerator implemented on Xilinx XCZU7EV performs 54.5× faster than CPU and 35.2× more energy-efficient than GPU.