Demo Data from VLDB 2026 / reviewers in the wild / expert
François Carouge
dblp:15/8375
· DBLP profile ↗
2ranked-venue papers
1as first author
0since 2021 · last 2011
—ORCID · none
Domains — the database's venue-derived domains; a paper can count in several
Systems, architecture and hardware · 1Software engineering, systems software and programming languages · 1
Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.
| Software engineering, system software, and programming languages
1 paper |
Concurrent programming · 100% | |
| Computer architecture, parallel and distributed computing, and storage systems
1 paper |
Parallel and multicore computing · 100% |
Topics — the 4 heaviest of 4, each with the papers that count most for it
| Topic | Weight | Papers | Last | Evidence papers |
|---|---|---|---|---|
Concurrent programming › transactional memory
hybrid transactional memory |
0.1 | 1 | 2011 | Hybrid NOrec: a case study in the effectiveness of best effort hardware transactional memory · ASPLOS 2011 |
Concurrent programming
transactional memory |
0.1 | 1 | 2011 | Hybrid NOrec: a case study in the effectiveness of best effort hardware transactional memory · ASPLOS 2011 |
Parallel and multicore computing › transactional memory
hardware transactional memory |
0.1 | 1 | 2011 | Hybrid NOrec: a case study in the effectiveness of best effort hardware transactional memory · ASPLOS 2011 |
Concurrent programming › transactional memory
software transactional memory |
0.0 | 1 | 2011 | Hybrid NOrec: a case study in the effectiveness of best effort hardware transactional memory · ASPLOS 2011 |
Methods — techniques the papers use, named apart from their topics
transactional memory · 0.2simulation · 0.2
| Year | Publication | Venue | Position |
|---|---|---|---|
| 2011 | Hybrid NOrec: a case study in the effectiveness of best effort hardware transactional memoryabstractTransactional memory (TM) is a promising synchronization mechanism for the next generation of multicore processors. Best-effort Hardware Transactional Memory (HTM) designs, such as Sun's prototype Rock processor and AMD's proposed Advanced Synchronization Facility (ASF), can efficiently execute many transactions, but abort in some cases due to various limitations. Hybrid TM systems can use a compatible software TM (STM) in such cases. Luke Dalessandro, François Carouge, Sean White, Yossi Lev, Mark Moir, Michael L. Scott, Michael F. Spear |
ASPLOS | 2 |
| 2010 | A Scalable Lock-Free Universal Construction with Best Effort Transactional Hardware
François Carouge, Michael F. Spear |
DISC | 1 |