This paper describes a bus design rule checking method which efficiently checks whether signal conflicts may occur on the tri-state buses in a given circuit and whether the buses may be in floating states. By using BDD (binary decision diagram) representations, a practical bus design rule check program has been obtained.

A practical rule-based testability rule checker for VLSI testing adopting a tunable rule-base shell suited for rule checking is described. The checking process is divided into symbolic simulation and violation detection. The testability rules applied in the violation detection and the circuit primitive operation rules applied in the symbolic simulator are treated as rule bases. Circuit primitives and symbolic signal values described in the rules can also be predefined by testability rule engineers.>

This paper describes an automatic test generation system which effectively generates test vectors by recognizing the circuit blocks for which vectors are automatically generated and the circuit blocks for which vectors have to be manually prepared.

Describes a test generation and fault simulation method which detects faults in the clock control logic that can cause register initialization failure in sequential circuits. By assigning an individual initial value X/sub n/ to the inaccessible register n in the faulty circuit and observing both the fault signal 0/X/sub n/ (0 in the good circuit/X/sub n/ in the faulty circuit) and 1/X/sub n/ in a different time frame, test vectors which can detect previously undetectable faults can be generated. Consequently, this method can generate test vectors with 98% to 100% fault coverage for sequential circuits for which conventional test generation methods only achieve 89% to 95% coverage.>

This paper deals with an LSI design management system which automates CAD program performance analysis. CAD program/library version control, design process control, design cost estimation and the collection of such statistical information as the sizes of the circuits being designed. The design management automation has been accomplished by analyzing statistical and control information generated by all the CAD programs and the operating system.

For ECL circuits. DC parametric tests such as input current (IIL IIH), reference voltage (VBB), and power supply current (ICC) tests are executed as well as functional tests.