Logic density increases have made feasible the implementation of multiprocessor systems able to meet the intensive data processing demands of highly concurrent systems. We describe the research and hardware implementation of a high-performance parallel multicompressor chip. A detailed investigation into the performances of alternative input and output routing strategies for realistic data sets demonstrate that the design of parallel compression devices involves important trade offs that affect compression performance, latency, and throughput. The most promising approach is implemented into FPGA hardware and is shown to provide a scalable compression solution at throughputs able to cope with the demands of modern high-bandwidth applications.

This paper presents the X-MatchPRO high-speed lossless data compression algorithm and its hardware implementation, which enables data independent throughputs of 1.6 Gbit/s compression and decompression using contemporary low-cost reprogrammable field-programmable gate array technology. A full-duplex implementation is presented that allows a combined compression and decompression performance of 3.2 Gbit/s. The features of the compression algorithm and architecture that have enabled the high throughputs are described in detail. A comparison between this device and other commercially available data compressors is made in terms of technology, compression ratio, and throughput. X-MatchPRO is a fully synchronous design proven in silicon specially targeted to improve the performance of Gbit/s storage and communication applications.

This paper presents a high-performance application specific architecture for real time lossless data compression, which enables data throughputs over 1.5 Gbits/s compression and decompression using contemporary low-cost re-programmable FPGA technology. The implementation is embedded into a PCI-based system and tested at speed using a PC as the host computer.. A single FPGA is used to map all the functions in the system including the compression and decompressor cores, DMA logic, control logic and Master/Target PCI core. The independent compression and decompression channels enable a combined compression and decompression performance over 3 Gbits/s and robust self-checking hardware where each compress block can be automatically decompressed to defect hardware failures or errors introduced by the communication channel.

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