Software Ecosystem (SECO) has emerged as a crucial concept, which represents a collaborative and interconnected environment in which a variety of actors engage in developing software systems. SECOs play a key role in the development of Cyber-Physical Systems (CPSs), that present a myriad of challenges, primarily due to the need for real-time responsiveness, reliability, security, and interoperability. The implications of leveraging SECOs for developing CPSs are profound in both research and practice. This paper aims to understand the collaboration between industry and academia within SECOs for the development of CPSs, identifying potential challenges and providing insights and guidelines for the proper management of these collaborations. We conducted a systematic literature review (SLR), complemented by empirical evidence collected through an opinion survey administered to the partners of the European collaborative project AIDOaRt, a concrete example of a SECO, which worked on the development of CPSs. From these findings we discuss the identified challenges, and potential effects on collaboration, in addition to our lessons learned in the AIDOaRt project and SECO.

Digital twins are virtual representations of real-world entities or systems. Their primary goal is to help organizations understand and predict the behaviour and properties of these entities or systems. Additionally, digital twins enhance activities such as monitoring, verification, validation, and testing. However, the inherent complexity of digital twins implies challenges throughout the systems engineering process. This notably includes design, development, and analysis phases, as well as deployment, execution, and maintenance. Moreover, existing approaches, methods, techniques, and tools for modelling, simulating, validating, and monitoring single digital twins must now address the increased complexity in federation scenarios. These scenarios introduce new challenges, such as digital twin identification, shared metadata, cross-digital twin communication and synchronization, and federation governance. The KDT Joint Undertaking MATISSE project tackles these challenges by aiming to provide a model-driven framework for the continuous engineering of federated digital twins. It leverages model-driven engineering techniques and practices as the core enabling technology, with traceability serving as an essential infrastructural service for the digital twins federation. In this paper, we introduce the MATISSE conceptual framework for digital twins, highlighting both the novelty of the project's concept and its technical objectives. As the project is still in its initial phase, we identify key research challenges relevant to the DATE community and propose a preliminary research roadmap. This roadmap addresses traceability and federation mechanisms, the required continuous engineering strategy, and the development of digital twin-based services for verification, validation, prediction, and monitoring. To illustrate our approach, we present two concrete scenarios that demonstrate practical applications of the MATISSE conceptual framework.

Context: Due to the proliferation of generative AI models in different software engineering tasks, the research community has started to exploit those models, spanning from requirement specification to code development. Model-Driven Engineering (MDE) is a paradigm that leverages software models as primary artifacts to automate tasks. In this respect, modelers have started to investigate the interplay between traditional MDE practices and Large Language Models (LLMs) to push automation. Although powerful, LLMs exhibit limitations that undermine the quality of generated modeling artifacts, e.g., hallucination or incorrect formatting. Recording modeling operations relies on human-based activities to train modeling assistants, helping modelers in their daily tasks. Nevertheless, those techniques require a huge amount of training data that cannot be available due to several factors, e.g., security or privacy issues. Objective: In this paper, we propose an extension of a conceptual MDE framework, called MASTER-LLM, that combines different MDE tools and paradigms to support industrial and academic practitioners. Method: MASTER-LLM comprises a modeling environment that acts as the active context in which a dedicated component records modeling operations. Then, model completion is enabled by the modeling assistant trained on past operations. Different LLMs are used to generate a new dataset of modeling events to speed up recording and data collection. Results: To evaluate the feasibility of MASTER-LLM in practice, we experiment with two modeling environments, i.e., CAEX and HEPSYCODE, employed in industrial use cases within European projects. We investigate how the examined LLMs can generate realistic modeling operations in different domains. Conclusion: We show that synthetic traces can be effectively used when the application domain is less complex, while complex scenarios require human-based operations or a mixed approach according to data availability. However, generative AI models must be assessed using proper methodologies to avoid security issues in industrial domains.

Modern real-time embedded systems increasingly use runtime reconfigurable architectures to reduce size, weight, and power while ensuring predictability. However, reconfiguration delay is non-negligible and varies due to resource contention. Unlike existing solutions that affect system resources or timing, this paper presents an approach and tools to provide a safe, tight reconfiguration delay bound by accurately modeling contention, without additional resource usage, and applicable to most embedded Systems-on-Chip. Additionally, by using Quality-of-Service mechanisms available in modern systems-on-chip, the proposed approach allows designers to set an upper limit for the reconfiguration delay and maintain it against interference from competing tasks. To evaluate the proposed approach, we present two experiments in which it is applied to a representative configuration on a Xilinx Zynq UltraScale+ platform. Experimental results indicate that the reconfiguration delay bound holds under induced worst-case interference scenarios, ensuring that, under heavy workload conditions, the reconfiguration delay can be up to 6.3 times its value in isolation. Moreover, the approach can automatically generate a quality-of-service configuration that ensures a maximum reconfiguration delay 1.8 times its value in isolation, with only a 14% slowdown on contenders and no additional resource consumption, outperforming the existing state of the art. • An approach to emulate worst-case contention for Dynamic-Partial Reconfiguration. • A tool to inject traffic and characterize Dynamic Partial Reconfiguration delay. • QoS-based mitigation ensuring timing isolation for Dynamic Partial Reconfiguration.

As embedded systems are required to satisfy increasing functional and non-functional requirements, heterogeneous systems-on-chip architectures are progressively adopted. While these complex systems-on-chip deliver high performance, they require efficient coordination of the tasks they carry out. To tackle this challenge, designers often resort to runtime mechanisms allowing the dynamic alignment of application requirements with platform services. In turn, runtime mechanisms require the adoption of on-chip monitoring systems. The integration of on-chip monitoring systems into a system-on-chip results in a monitored system-on-chip. Notwithstanding, this integration risks driving a re-design and a re-implementation of the whole system-on-chip, potentially driving to a time-to-market deadline miss. In the literature, HW/SW co-design approaches for monitored systems-on-chip have been proposed to overcome the problem. However, the existing HW/SW co-design approaches prevent performing a system-level design-space exploration that involves all the monitoring requirements, and they also prevent adequate reuse of existing on-chip monitoring systems. This article proposes an approach for efficient HW/SW co-design of monitored systems-on-chip, aiming to comprehensively capture all monitoring requirements at the system-level and to perform a system-level design-space exploration to satisfy them, enforcing the reuse of existing on-chip monitoring systems. The proposed approach is validated through two experimental activities, which demonstrate a 24% reduction in total development time for a monitored system-on-chip implemented on FPGA, compared to the customary approach. The results also show that the approach reduces the risk of missing time-to-market deadlines, supports flexible design choices, and enables the reuse of on-chip monitoring systems.

Electronic Design Automation (EDA) is a crucial research area related to the development of electronic systems. In particular, High-Level Synthesis (HLS) simplifies HW design by automatically translating C/C++/System C specifications into HW description languages. However, HLS for large systems can be time-consuming. In recent years, Machine Learning (ML) has emerged as a prominent topic in EDA, with numerous studies demonstrating its potential to enhance EDA methods covering nearly all phases of the HW design flow. In such a context, this work presents an approach and related frameworks to collect datasets (i.e., SLIDE-x) useful for performing HLS timing and resource estimation through ML techniques (i.e., SLIDE-x-ML), introducing a data-driven component for feature creation that enhances predictions through various input representations and ML methods.

Producing accurate software models is crucial in model-driven software engineering (MDE). However, modeling complex systems is an error-prone task that requires deep application domain knowledge. In the past decade, several automated techniques have been proposed to support academic and industrial practitioners by providing relevant modeling operations. Nevertheless, those techniques require a huge amount of training data that cannot be available due to several factors, e.g., privacy issues. The advent of large language models (LLMs) can support the generation of synthetic data although state-of-the-art approaches are not yet supporting the generation of modeling operations. To fill the gap, we propose a conceptual framework that combines modeling event logs, intelligent modeling assistants, and the generation of modeling operations using LLMs. In particular, the architecture comprises modeling components that help the designer specify the system, record its operation within a graphical modeling environment, and automatically recommend relevant operations. In addition, we generate a completely new dataset of modeling events by telling on the most prominent LLMs currently available. As a proof of concept, we instantiate the proposed framework using a set of existing modeling tools employed in industrial use cases within different European projects. To assess the proposed methodology, we first evaluate the capability of the examined LLMs to generate realistic modeling operations by relying on well-founded distance metrics. Then, we evaluate the recommended operations by considering real-world industrial modeling artifacts. Our findings demonstrate that LLMs can generate modeling events even though the overall accuracy is higher when considering human-based operations. In this respect, we see generative AI tools as an alternative when the modeling operations are not available to train traditional IMAs specifically conceived to support industrial practitioners.

Summary Cyber‐physical systems (CPSs) are increasing in developmental complexity. Several emerging technologies, such as Model‐based engineering, DevOps, and Artificial intelligence, are expected to alleviate the associated complexity by introducing more advanced capabilities. The AIDOaRt research project investigates how the aforementioned technologies can assist in developing complex CPSs in various industrial use cases. In this paper, we discuss the experiences of industry and academia collaborating to improve the development of complex CPSs through the experiences in the research project. In particular, the paper presents the results of two working groups that examined the challenges of developing complex CPSs from an industrial and academic perspective when considering the previously mentioned technologies. We present five identified challenge areas from developing complex CPSs and discuss them from the perspective of industry and academia: data, modeling, requirements engineering, continuous software and system engineering, as well as intelligence and automation. Furthermore, we highlight practical experience in collaboration from the project via two explicit use cases and connect them to the challenge areas. Finally, we discuss some lessons learned through the collaborations, which might foster future collaborative efforts.

With the emergence of Cyber-Physical Systems (CPS), the increasing complexity in development and operation demands for an efficient engineering process. In the recent years DevOps promotes closer continuous integration of system development and its operational deployment perspectives. In this context, the use of Artificial Intelligence (AI) is beneficial to improve the system design and integration activities, however, it is still limited despite its high potential. AIDOaRT is a 3 years long H2020-ECSEL European project involving 32 organizations, grouped in clusters from 7 different countries, focusing on AI-augmented automation supporting modelling, coding, testing, monitoring and continuous development of Cyber-Physical Systems (CPS). The project proposes to apply Model-Driven Engineering (MDE) principles and techniques to provide a framework offering proper AI-enhanced methods and related tooling for building trustable CPSs. The framework is intended to work within the DevOps practices combining software development and information technology (IT) operations. In this regard, the project points at enabling AI for IT operations (AIOps) to auto-mate decision making process and complete system development tasks. This paper presents an overview of the project with the aim to discuss context, objectives and the proposed approach.

During the initial design phases of an embedded system, the ability to support designers using metrics, obtained through a preliminary analysis, is of fundamental importance. Knowing which initial parameters of the embedded system (HW or SW) influence such metrics is even more important. The main characteristic of an embedded system that typically designers need to measure is the embedded SW (i.e., functions) execution time, used to describe the final system's performance (i.e., timing performance metric). The evaluation of such a metric is often a critical task, relying on several different techniques at different abstraction levels. Furthermore, in the era of Big Data, the use of Machine Learning methods can be a valid alternative to the classic methods used to evaluate or estimate metrics for temporal performance. In such a context, this paper describes a framework, based on the use of Machine Learning methods, to calculate a statement-level embedded software timing performance metric. Results are compared with those obtained with different approaches. They show that the proposed method improves the estimation accuracy for specific processor classes while also reducing estimation time.

The purpose of this paper is to introduce run time monitoring infrastructures and to analyze trace data inside a well-established component-based methodology. The goal is to show the concept among different monitoring requirements by defining a general reference architecture that can be adapted to different scenarios. Starting from design artifacts, generated by a system engineering modeling tool, and source code automatically generated from UML models, a custom Hardware monitoring sub-system infrastructure will be presented. This sub-system will be able to generate run-time artifacts for run-time verification. We will show how the framework provides round-trip support in the development chain, injecting monitoring requirements from design models down to code and its execution on the platform and trace data back to the models, where the expected behavior will then be compared with the actual behavior. This approach will be used towards optimizing design models for specific properties (e.g, for system performance), using a specific constraint approach compliant with UML standards. Industrial and custom use cases will be used to demonstrate the effectiveness of this approach in real scenarios.

Heterogeneous parallel devices are becoming widely diffused in the embedded systems application field since they allow to improve time performances and other orthogonal metrics (e.g., cost, power, size, etc.) at the same time. In such a context, the introduction of safety requirements, as dictated by the relevant standards (i.e., DO-178 B/C and RTCA/DO-254 in airborne systems, ARINC 653 for avionics software, ISO-26262 in automotive domain, etc.) while considering shared resources on a heterogeneous parallel HW platform, adds further challenges to industrial and academic research. This kind of platforms that execute tasks with different levels of criticality are commonly called mixed-criticality embedded systems. So, the main problem in their management is to ensure that low criticality tasks do not interfere with high criticality ones. The final goal is to allow several applications to interact and coexist on the same platform. For this, the exploitation of virtualization technologies (i.e., hypervisors) allows to guarantee isolation and to satisfy certification requirements but introduces scheduling overhead and new HW/SW partitioning challenges. In such a scenario, this work focuses on a framework for modeling, analysis, and validation of mixed-criticality and real-time systems based on an existing "Model-Based Electronic System Level HW/SW Co-Design" methodology. The main contribution of this work is the integration of the considered framework with Xamber tool in order to provide systems implementations by exploiting a design space exploration able to consider Xtratum-based SW partitions.

This work faces the role of Design Space Exploration for embedded systems based on heterogeneous parallel architectures and subject to mixed-criticality system requirements, while considering the exploitation of hypervisor-based SW partitions to better manage isolation. In particular, it presents an evolutionary partitioning and mapping approach integrated into a reference Electronic System Level HW/SW Co-Design framework to propose and early validate design solutions by means of HW/SW Co-Simulations.

Nowadays embedded systems are powerful and everywhere. They implement complex functionality relying on a huge set of different hardware and software (HW/SW) architectures. In order to reduce their development effort, HW/SW Co-Design techniques are used during the entire development cycle. These techniques aim at helping designers to define a feasible hardware and software partitioning for the system in such a way that functional and non-functional requirements are fulfilled. In this context Design Space Exploration is a challenging activity since a huge number of different implementation alternatives need to be evaluated.

Timing analysis of embedded systems is an operation performed when there are tasks that have to execute with a well precise deadline, and need to be scheduled, such as those on real-time systems. The diffusion of embedded systems to different kind of application areas is driving platforms toward heterogeneous multi-core architectures, that require a timing analysis done by using measurement based techniques. Measurements collection, when done via an instrumentation of the application, can cause an overhead in the execution time, footprint and necessary space to store data, that can affect the behaviour of the system. In such a scenario, this work proposes a framework that allows a user to quickly perform instrumentation choices, by using a concept named Time Band, and to have a direct feedback about the impact of its choices on some performance parameters. Time Band is then applied to Rapitime, a diffused timing analysis tool, and first tests have been done on IA-32 and PowerPC architectures, showing the advantages of different techniques the can be applied to realize the framework.

In recent years, embedded applications have been characterized by increasingly stringent requirements, both from functional and non-functional point of view. This led to the adoption of complex hardware platforms (multi-core and many-core architectures), able to guarantee high computational power with low energy consumption and reduced footprint. An efficient characterization of these platforms can be problematic, given the large number of hardware resources and the complexity of software applications. For this reason, the need for a runtime analysis support should be taken in account during the design phase (a design "for monitorability"). This paper introduces "Adaptive Profiling Hardware Sub-system" (AIPHS), a hardware profiling tool supporting the development of runtime monitorable systems. Two different multicore platforms are considered in order to evaluate AIPHS functionalities: an asymmetric dual-MicroBlaze system and a quad-Leon3 system supporting symmetric multiprocessing.