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C. Glenn Shirley

dblp:150/7642 · DBLP profile ↗
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2ranked-venue papers
2as first author
0since 2021 · last 2014
—ORCID · none

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 2 · 2 first-author

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
1 paper
Hardware reliability and fault tolerance · 70% Memory systems · 23% Performance modeling and evaluation · 7%

Topics — the 5 heaviest of 5, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Memory systems
DRAM
0.212014
Copula Models of Correlation: A DRAM Case Study · IEEE Trans. Computers 2014
Hardware reliability and fault tolerance
fault tolerance techniques
0.212014
Copula Models of Correlation: A DRAM Case Study · IEEE Trans. Computers 2014
Hardware reliability and fault tolerance › memory reliability
retention time
0.212014
Copula Models of Correlation: A DRAM Case Study · IEEE Trans. Computers 2014
Hardware reliability and fault tolerance
soft errors
0.212014
Copula Models of Correlation: A DRAM Case Study · IEEE Trans. Computers 2014
Performance modeling and evaluation
workload characterization
0.112014
Copula Models of Correlation: A DRAM Case Study · IEEE Trans. Computers 2014

Methods — techniques the papers use, named apart from their topics

multivariate normal statistics · 0.2copula modeling · 0.2
YearPublicationVenuePosition
2014 Board manufacturing test correlation to IC manufacturing test
abstract
A large end-to-end database was created by joining an IC test factory database with a board contract manufacturer (CM) database using the unique electrical identity fused into the IC and read at IC and CM test steps. A new rank correlation method was used to measure statistical dependencies of IC failure rates in the CM factory on failure rates and attributes measured in the IC factory. IC factory dependency, including radial wafer symmetry, was seen in the CM data providing opportunity to improve CM failure rate at the cost of IC yield. A special kind of receiver operating characteristic (ROC) was constructed to quantify the IC factory yield cost of CM failure rate improvements for hypothetical IC factory screens additional to the screens which generated the database. A screen based on RAM fuse repair count was found to be better than one based on blocking of edge dies.
C. Glenn Shirley, W. Robert Daasch, Phil Nigh, Zoe Conroy
ITC1
2014 Copula Models of Correlation: A DRAM Case Study
abstract
Variable bit retention time observed in a 65-nm dynamic random access memory (DRAM) case study will cause miscorrelation between retention times occurring in Test and Use. Conventional multivariate normal statistics cannot adequately model this miscorrelation. A more general copula-based modeling approach, widely used in financial and actuarial modeling, solves this problem. The DRAM case study shows by example how to use copula models in test applications. The method includes acquiring data using a test vehicle, fitting the data to a copula-based statistical model, and then using the model to compute producer- and customer-oriented figures of merit of a product, different from the test vehicle. Different array sizes, fault tolerance schemes, test coverage, end-use (datasheet), and test condition specifications of the product are modeled.
C. Glenn Shirley, W. Robert Daasch
IEEE Trans. Computers1