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Ying-Chen Lin

dblp:151/3987 · DBLP profile ↗
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2ranked-venue papers
0as first author
1since 2021 · last 2021
—ORCID · conflict

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 1Applied, interdisciplinary, general and emerging computing · 1 · 1 since 2021

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
1 paper
Memory systems · 100%

Topics — the 2 heaviest of 2, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Memory systems
access latency reduction
0.212015
Improving DRAM latency with dynamic asymmetric subarray · MICRO 2015
Memory systems
DRAM
0.212015
Improving DRAM latency with dynamic asymmetric subarray · MICRO 2015

Methods — techniques the papers use, named apart from their topics

dynamic asymmetric subarray · 0.2
YearPublicationVenuePosition
2021 Fault-Tolerance Mechanisms for Software-Defined Internet of Vehicles
abstract
Due to the rapid development of the Internet of Things, cloud computing, big data, and software-defined networks technologies, vehicular ad hoc networks have evolved into software-defined Internet of Vehicles (IoV). In software-defined IoV, messages transmitted by vehicles are transferred using wireless communication technology, so attackers can easily attack specific vehicles and Road-Side Units (RSUs) within the wireless communication range. When any vehicle or RSU is under attack or control, the entire network may collapse and produce incorrect computing results, which in the worst case, can lead to car accidents. Therefore, building a highly reliable and fault-tolerant software-defined IoV is of high importance. In this paper, we visit the consensus problem in software-defined IoV. Software-defined IoV is built with infrastructures, that is, RSUs. RSUs have a backhaul capacity and a powerful computing capacity. Thus, in software-defined IoV, we will focus on how to use RSUs to assist vehicles in reaching a consensus.
Chien-Fu Cheng, Gautam Srivastava 0001, Jerry Chun-Wei Lin, Ying-Chen Lin
IEEE Trans. Intell. Transp. Syst.4
2015 Improving DRAM latency with dynamic asymmetric subarray
abstract
The evolution of DRAM technology has been driven by capacity and bandwidth during the last decade. In contrast, DRAM access latency stays relatively constant and is trending to increase. Much efforts have been devoted to tolerate memory access latency but these techniques have reached the point of diminishing returns. Having shorter bitline and wordline length in a DRAM device will reduce the access latency. However by doing so it will impact the array efficiency. In the mainstream market, manufacturers are not willing to trade capacity for latency. Prior works had proposed hybrid-bitline DRAM design to overcome this problem. However, those methods are either intrusive to the circuit and layout of the DRAM design, or there is no direct way to migrate data between the fast and slow levels.
Shih-Lien Lu, Ying-Chen Lin, Chia-Lin Yang
MICRO2