A novel design of RIS-assisted MIMO multiuser communication system using dirty paper coding (DPC) is presented in this paper. The design is applicable to any numbers of transmit and receive antennas and to any number of users, and requires only discrete phase shifts for RIS elements. For any given phase-configuration of RIS, the proposed design always achieves the corresponding channel capacity. The proposed framework involves two alternating optimization steps. Initially, we optimize the input covariance matrices of DPC encoders to maximize the sum-rate of downlink communication while keeping the RIS coefficient matrix fixed. Subsequently, we employ the alternating direction method of multipliers to identify optimal discrete RIS phases that maximize an upper bound on the sum-rate, with the DPC covariance matrices fixed. Simulation results show that the proposed design is highly robust and delivers near optimal sum-rate performance using only quad-phases for RIS elements.

Singe-Electron Transistor (SET) is considered as a promising candidate of low-power devices for replacement or co-existence with Complementary Metal-Oxide-Semiconductor (CMOS) transistors/circuits. In this work, we propose a diagnosis approach for SET array under a more generalized defect model. With the more generalized defect model, the diagnosis approach will become more practical but complicated. We conducted experiments on a set of SET arrays with different dimensions and defect rates. The experimental results show that our approach only has 3.8% false-negative rate and 0.7% misjudged-category rate on average without reporting any false-positive edge when the defect rate is 4%. Therefore, the proposed diagnosis approach can diagnose the defective SET arrays and elevate the reliability of the SET arrays in the synthesis flow.

The identification of threshold function (TF), which determines whether a Boolean function can be represented by an linear threshold logic gate (LTG) or not, is a fundamental but important task in the theories of threshold logic. In this paper, we propose a more efficient and effective algorithm of TF identification by constructing the system of irredundant inequalities and adjusting the weight assignment comprehensively. This is the first non-ILP-based approach that is able to identify all the eight-input TFs. The experimental results demonstrated that the proposed approach is more effective than all the existing non-ILP-based approaches and the LTGs obtained by the proposed approach are optimal for near 100% cases. For TFs with 9–15 inputs, the proposed approach can identify 100 000 randomly generated TFs as well in a reasonable CPU time.

Recently, Threshold logic attracts a lot of attention due to the advances of its physical implementation and the strong binding to neural networks. Approximate computing is a new design paradigm that focuses on error-tolerant applications, e.g., machine learning or pattern recognition. In this paper, we integrate threshold logic with approximate computing and propose a synthesis algorithm to obtain cost-efficient approximate threshold logic circuits with an error rate guarantee. We conduct experiments on IWLS 2005 benchmarks. The experimental results show that the proposed algorithm can efficiently explore the approximability of each benchmark. For a 5% error rate constraint, the circuit cost can be reduced by up to 65%, and 22.8% on average. Compared with a naive method, our approach has a speedup of 2.42 under a 5% error rate constraint.

Boolean Relation (BR) is a many-to-many mapping between two domains. Logic optimization considering BR can exploit the potential flexibility existed in logic networks to minimize the circuits. In this paper, we present a logic optimization approach considering BR. The approach identifies a proper sub-circuit and locally changes its functionality by solving the corresponding BR in the sub-circuit without altering the overall functionality of the circuit. We conducted experiments on a set of MCNC benchmarks that cannot be further optimized by resyn2 script in ABC. The experimental results show that the node counts of these benchmarks can be further reduced. Additionally, when we apply our approach followed by the resyn2 script repeatedly, we can obtain 6.11% improvements in average.

Fault-based verification technique is a method to qualify a verification environment. The better verification environment can detect output differences between the fault-free and fault-injected circuits with a higher probability. Since different injected faults could cause the same output response under all stimuli, which are called equivalent faults, maximally identifying these equivalent faults can improve the efficiency of verification environment qualification without sacrificing its quality. The 2016 CAD Contest at ICCAD posed the problem of identifying equivalent faults in the circuits. This paper presents our work in the Contest with some improvements.

Memristor, which is a two-terminal nanodevice, widely used in various fields, e.g., machine learning and neuromorphic systems, has attracted much attention these years. Memristor can also be used to realize an implication logic gate and thus logic circuits. However, the fanouts in a memristor-based logic circuit have some constraints and need to be processed with special care. On the other hand, in addition to the number of memristors, the number of operational pulses is another metric to measure the quality of a memristor-based logic circuit. Hence, in this paper, we propose a synthesis algorithm to deal with the fanout problems in memristor-based logic circuits using implication logic gates for having a minimal number of operational pulses. We conducted experiments on a set of MCNC benchmarks. The experimental results show that the proposed algorithm can reduce 29% operational pulses and 36% memristor count on average compared with the state-of-the-art.

Quantum-dot Cellular Automata (QCA) has emerged as a new design paradigm for nanotechnologies. Since the operational logic in QCA is the majority logic, much research about the synthesis and optimisation of majority logic has been proposed recently. In this paper, we propose an optimisation method by merging nodes in the Majority-Inverter-Graph, which is the representation of majority logic circuits. Instead of using satisfiability solvers, our approach can identify the node mergers by using logic implications for circuit size reduction. The experimental results show that for a set of EPFL benchmarks, our approach can minimise the node count by 21% when integrated with the state-of-the-art on average.

Single-electron transistor (SET) at room temperature has been demonstrated as a promising device for extending Moore's law due to its ultralow-power consumption. Previous works proposed mapping approaches to implement Boolean functions on SET arrays. However, these approaches were based on an ideal assumption that the SET arrays are defect-free. Recently, a diagnosis method was proposed targeting at defective SET arrays. However, the approach was static, such that the performance is inefficient. As a result, in this paper, we propose a dynamic diagnosis approach that can efficiently identify the locations and the types of the defects in the SET arrays. The experimental results show that the proposed dynamic diagnosis approach can achieve the same results as the previous work with much less CPU time on a set of benchmarks. Furthermore, the proposed method spent a few seconds while the previous work exceeded the CPU time limit of 3600 s on some benchmarks.

Traceroute is a very useful troubleshooting tool. It reveals the routing path taken by a packet destined to a remote host. Traceroute is originally designed for the legacy IP network. However, the mechanism used by it does not work in an SDN network. In an SDN network, there has been a similar tool called SDN traceroute that provides similar functions as traceroute. However, SDN traceroute does not work in the legacy IP network. Nowadays, hybrid networks composed of both legacy and SDN switches are expected to exist for several years during the transition period. For such a hybrid network, we design and implement a tool called hybridtrace that can reveal the routing path taken by a packet that needs to traverse multiple legacy network islands and SDN network islands to reach its destination. In this paper, we present the design and implementation of hybridtrace, show the path-tracing information provided by it, and demonstrate its functions and operations.

In this paper, we design and implement a scheme to build an optimal spanning tree over a hybrid network composed of SDN and legacy switches. SDN is an emerging network technology and gradually gaining adoption worldwide. However, during the technology transition period, which may last several years from now on, inevitably SDN switches and legacy switches will need to coexist in a network. In a legacy network with loops, the IEEE 802.11D distributed spanning tree protocol is used to construct a spanning tree to avoid the packet broadcast storm problem. In an SDN network, the SDN controller can use the collected global knowledge of the network topology to centrally construct a spanning tree to solve this problem. However, so far there is no scheme to integrate together the spanning trees separately built in multiple isolated legacy networks and isolated SDN networks to build an optimal spanning tree across the hybrid network. Our scheme presented in this paper is the first scheme designed and implemented for this purpose. In this paper, we used the EstiNet OpenFlow network simulator and emulator to simulate hybrid networks. Our scheme is implemented as a module of the Floodlight SDN controller to construct an optimal spanning tree over the simulated hybrid networks. Our simulation results show that our scheme can correctly generate an optimal spanning tree based on two performance metrics: the average path latency and the average path throughput of a spanning tree.

The improvement of sanitary conditions and changes of life style making people's health awareness began to rise. The progress of medical and the promotion of medicine and health, the concept of preventive healthcare is widespread. People begin to concern about the quality of the environment where they stayed. The environmental comfort index include temperature, related humidity, illumination, noise and carbon dioxide. Among these, we monitor and record the values of temperature, related humidity and carbon dioxide. In this paper, we built an environment quality monitoring system, which can adjust the air quality in door and monitor the concentration of harmful gases like formaldehyde, volatile organic compounds and carbon monoxide. If the environment comfort value is not up to standard, the related equipment will be turned on. The system will alert if the content of harmful gases exceed the standard. We hope that based on these real-time data, the proposed system can help people make right and timely decisions, and act on time to maintain a beneficial environment in the monitored area.

Along with the improvement of sanitary conditions and changes of life style, people begin to pay attention to the modern concept of health promotion and preventive medicine. Therefore, we built an intelligent environment monitoring feedback system to collect data of physical conditions of employees and air conditions of the working environment, displayed the collected data with a real time interface, and sent out warming messages to prevent accidents. We hope that based on these real-time data, the proposed system can help people make right and timely decisions, and act on time to maintain a beneficial environment in the monitored area.