VLDB 2026 Research / reviewers in the wild / expert
David Carl Karlgaard
dblp:151/5366
· DBLP profile ↗
1ranked-venue papers
0as first author
0since 2021 · last 1974
—ORCID · none
Domains — the database's venue-derived domains; a paper can count in several
Systems, architecture and hardware · 1
Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.
| Computer architecture, parallel and distributed computing, and storage systems
1 paper |
Processor architecture and microarchitecture · 88% Electronic design automation · 12% |
Topics — the 4 heaviest of 4, each with the papers that count most for it
| Topic | Weight | Papers | Last | Evidence papers |
|---|---|---|---|---|
Processor architecture and microarchitecture › microprogramming
microcode generation |
0.0 | 1 | 1974 | Heuristic Synthesis of Microprogrammed Computer Architecture · IEEE Trans. Computers 1974 |
Processor architecture and microarchitecture
microprogramming |
0.0 | 1 | 1974 | Heuristic Synthesis of Microprogrammed Computer Architecture · IEEE Trans. Computers 1974 |
Processor architecture and microarchitecture › special-purpose processor › application-specific processor design
instruction synthesis |
0.0 | 1 | 1974 | Heuristic Synthesis of Microprogrammed Computer Architecture · IEEE Trans. Computers 1974 |
Electronic design automation
logic synthesis |
0.0 | 1 | 1974 | Heuristic Synthesis of Microprogrammed Computer Architecture · IEEE Trans. Computers 1974 |
Methods — techniques the papers use, named apart from their topics
iterative algorithm · 0.0heuristic synthesis · 0.0
| Year | Publication | Venue | Position |
|---|---|---|---|
| 1974 | Heuristic Synthesis of Microprogrammed Computer ArchitectureabstractThis paper describes an algorithm for the synthesis of applications-oriented microcode for a dynamically microprogrammable computer. The synthesis algorithm provides an iterative method for generating specialized architectures. Current attempts at generating specialized architectures can be considered as manual tuning due to human generation of specialized microcode. Heuristic instruction synthesis is described as one phase of a heuristic tuning process which attempts to automate the manual tuning process. Abd-Elfattah Mohamed Abd-alla, David Carl Karlgaard |
IEEE Trans. Computers | 2 |