Recent research in electronic design automation (EDA) tools has focused on utilizing artificial intelligence (AI) for sizing analog circuit designs. Still, there has been a lack of focus on optimizing complex analog circuits. To optimize complex analog circuits within a few circuit simulations, we propose a partition-and-conquest-based optimizer (PC-Opt). PC-Opt assigns distinct actor-critic roles within a multi-agent system, facilitating the partitioning of complex analog circuits and conquering their optimization challenges. Partial differential training is developed for the proper prediction of each actor, which merges each other and then predicts the optimized entire circuit. To generate a compact and non-biased dataset for network training, a concentrated sampling method is devised. Experimental results on three circuits demonstrate the effectiveness of PC-Opt.

We propose a Diffusion-Enhanced Graph Transformer (DEGT) for analog circuit optimization that overcomes the limitations of traditional vector- and graph-based approaches. Conventional methods struggle to capture the complex connectivity of analog circuits and often require expert-imposed heuristic constraints on the sizing of some transistors to greatly reduce the searching space. In contrast, our method introduces three key innovations. First, an enhanced graph representation combined with a transformer architecture conveys circuit information to the machine learning network without any loss, enabling effective incremental knowledge transfer across various circuit designs. Second, the proposed DEGT quantifies the influence of each device by considering connection distances and path configurations, thereby providing a comprehensive, topology-aware representation of device interactions. Third, a violation handling method autonomously trains non-functional regions in the design space, eliminating the need for expert-imposed constraints or circuit classifications. Experimental evaluations demonstrate that the proposed optimizer consistently improves the figure of merit for a circuit with each round of incremental knowledge transfer using data from different circuits. These results highlight the potential of our approach to advance autonomous analog circuit design by reducing the reliance on expert intervention and improving overall optimization performance.

Finding an optimal point in the design space of analog circuits requires a substantial time-consuming effort even for skillful circuit designers. There have been extensive studies on automated sizing of transistors in analog circuits based on machine learning (ML) algorithms. However, the previous approaches suffer from lack of expandability and necessitate an inevitable retraining process of the given model to apply for optimization of different circuits. The graph-based representation of a circuit with reinforcement learning (RL) achieved a knowledge transfer when optimizing the same circuit with different process technologies. However, it can be hardly applied to different circuit topologies due to the failure of generalizing the training of RL agent. This paper introduces Trans-Net, an analog circuit optimizer that is capable of supporting the knowledge transfer across different circuits as well as different process technologies with a circuit representation that defines the circuit topology by one-to-one mapping from SPICE netlist. The proposed analog circuit optimizer successfully supports multiple circuits within a single ML model, showcasing its effectiveness on five different circuit topologies across three different process technologies.

There is a need for electronic design automation (EDA) tools for analog circuit design since analog circuit design requires substantial human effort and expertise. Using reinforcement learning (RL)-inspired methodologies, this study presents MA-Opt, an analog circuit optimizer. We propose MA-Opt to provide multiple predictions of optimized circuit designs through the use of multiple actors. Multiple actors can be exploited effectively by sharing a memory that affects the loss function of network training, resulting in an accelerated optimization of circuits. Furthermore, we introduce a cooperative near-sampling method deploying a synergistic effect and then optimizing the design. The efficiency of MA-Opt was demonstrated by simulating three analog circuits and comparing the results to other methods. In the experiment, the use of multiple actors with a shared elite solution set and the cooperative near-sampling method proved to be effective. MA-Opt achieved minimum target metrics up to 34$\%$better than DNN-Opt within the same number of simulations while satisfying all given constraints. Moreover, at identical runtime, MA-Opt exhibited better Figure of Merits (FoMs) in comparison to DNN-Opt.

Designing analog circuits incurs high time costs because designers must consider numerous design variables or trade-off relationships of circuit performance based on a lot of knowledge and experience. To reduce design time, various machine learning methods have been used to optimize analog circuits by learning the correlation between the device size and the circuit performance. However, it is difficult to train the correlation because of its high non-linearity and wide design space. In this paper, this study proposes a new framework to optimize analog circuit designs by combining reinforcement learning (RL) and the sensitivity analysis with gm/IDsizing, which is more intuitive for interpreting circuit performance. Furthermore, the universal value function approximator (UVFA), previously proposed in RL, is modified more simply to make it easier to find the target design. Additionally, the dataset is rearranged and sampled by the criteria that are established based on the principle of circuit operation, which helps to orient the agent to learn the circuit operation. Using the proposed methods, we optimize three types of differential amplifiers with common mode feedback circuits and obtain the best circuit design. Compared to baseline, we find the optimal point using modified UVFA, and moreover, reduce the number of iterations by 42.2%, 39.5%, and 37.5%, respectively, for the three test cases.

Analog circuit design requires significant human efforts and expertise; therefore, electronic design automation (EDA) tools for analog design are needed. This study presents MA-Opt that is an analog circuit optimizer using reinforcement learning (RL)-inspired framework. MA-Opt using multiple actors is proposed to provide various predictions of optimized circuit designs in parallel. Sharing a specific memory that affects the loss function of network training is proposed to exploit multiple actors effectively, accelerating circuit optimization. Moreover, we devise a novel method to tune the most optimized design in previous simulations into a more optimized design. To demonstrate the efficiency of the proposed framework, MA-Opt was simulated for three analog circuits and the results were compared with those of other methods. The experimental results indicated the strength of using multiple actors with a shared elite solution set and the near-sampling method. Within the same number of simulations, while satisfying all given constraints, MA-Opt obtained minimum target metrics up to 24% better than DNN-Opt. Furthermore, MA-Opt obtained better Figure of Merits (FoMs) than DNN-Opt at the same runtime.

This paper proposes the design of a ternary inverter that uses low current as input voltage is VDD/2. When the supply voltage is set to 1 V, current supplied by a voltage source as an input voltage VDD/2 is reduced by 22.75% from 1.89μA to 1.46μA. By connecting ternary inverters back-to-back, a trit-storage element is implemented as a ternary SRAM cell. This paper also presents the first verification of read/write schemes that consider noise margins.

We propose an on-chip circuit technique to characterize jitter tolerance of binary clock and data recovery (CDR) circuit. The proposed jitter modulation scheme incorporates modulating-charge-pump and pulse-generator circuits to apply a periodic triangular voltage directly to the control voltage. The range of the modulated jitter amplitude is 0.05-2 UIpp at 10 MHz, and the frequency range is 100 KHz-20 MHz. The CDR circuit was fabricated in 65 nm CMOS, and the jitter tolerance was successfully measured at 5 Gbps with a 27-1 PRBS pattern, The accuracy is within 23% of the theoretical limit. The whole CDR circuit consumes 29.9mW at a supply voltage of 1.2 V.

This paper describes the characteristics of a half-rate clock-embedded source-synchronous signaling scheme to identify its constraints and to optimize the transceiver topology in the presence of a band-limited channel. The proposed signaling combines the half-rate clock to the common mode of the differential data with its mixing phase off by 0.5 UI. Two transceivers with resistive-load and inductive-load receivers are implemented in 130-nm CMOS technology to verify their feasibility for use as serial links. The prototype transceivers achieve a wide operating frequency range 2.25-6 and 5.6-8 Gb/s, respectively, satisfying bit error rate of-12measured at Tx-Rx linked configuration by 5-in-long FR4 trace with 231-1 PRBS. The power efficiencies of transceivers at maximum data rates are 6.4 and 4.6 mW/Gb/s, respectively.