Cryogenic power electronics has the potential to significantly improve Cyber Physical Systems (CPS) applications in aviation and space. However, their safety and reliability are yet to be studied systematically. To this end, we propose the first prototype of a deterministic toolchain for the design of Cryogenic Cyber Physical Systems (CCPS). Obviously, the design, verification and safety analysis of such systems pose considerable unknowns and challenges. Towards a potential solution, we propose an approach for unified functional safety, inspired by our earlier work. We leverage the recently developed deterministic framework (proposed by Google), called Logical Synchrony Networks, for distributed systems. This simplifies the modelling and safety analysis. Moreover, we propose a novel variant of Signal Temporal Logic (STL), called Synchronous Signal Temporal Logic (SSTL), which is specially tailored for CPS applications and designed using logical synchrony. We demonstrate the first prototype solution in the simulation of a CCPS system as a proof of concept.

Capsule networks (CapsNet) are a category of deep learning neural networks (DNN) that address one of the main issues and deficiencies of convolutional neural networks (CNN); loss of spatial information in pooling layers. However, the main concern with CapsNets is their compute-intensive nature, which is mainly related to the vector-based calculations during dynamic routing and acts as a barrier for their deployment in real-time applications. To address the specific computing requirements of dynamic routing in capsule layers of CapsN ets, we develop a hardware accelerator for dynamic routing using Vitis HLS. In this paper, we present a hardware acceleration solution for capsule networks by integrating AMD Xilinx deep processing unit (DPU) and a custom accelerator for the capsule layer. Our results show significant improvement in throughput compared with the baseline implementation when CapsNet is implemented on Zynq UltraScale+ MPSoC ZCU102 usinz Vitis AI DPUs.

Modern cars are being equipped with powerful computational resources for autonomous driving systems (ADS) as one of their major parts to provide safer travels on roads. High accuracy and real-time requirements of ADS are addressed by HW/SW co-design methodology which helps in offloading the computationally intensive tasks to the hardware part. However, the limited hardware resources could be a limiting factor in complicated systems. This paper presents a dynamically reconfigurable system for ADS which is capable of real-time vehicle and pedestrian detection. Our approach employs different methods of vehicle detection in different lighting conditions to achieve better results. A novel deep learning method is presented for detection of vehicles in the dark condition where the road light is very limited or unavailable. We present a partial reconfiguration (PR) controller which accelerates the reconfiguration process on Zynq SoC for seamless detection in real-time applications. By partially reconfiguring the vehicle detection block on Zynq SoC, resource requirements is maintained low enough to allow for the existence of other functionalities of ADS on hardware which could complete their tasks without any interruption. Our presented system is capable of detecting pedestrian and vehicles in different lighting conditions at the rate of 50fps (frames per second) for HDTV (1080x1920) frame.

Pedestrian detection is one of the most challenging and vital tasks of driver assistance systems (DAS). Among several algorithms developed for human detection, histogram of oriented gradients (HOG) followed by support vector machine (SVM) has shown the most promising results. This paper presents a hardware accelerator for real-time pedestrian detection at different scales to fulfill the real-time requirements of DAS. It proposes an algorithmic modification to the conventional multi-scale object detection by means of HOG+SVM to increase the throughput and maintain the accuracy reasonably high. Our hardware accelerator detects pedestrians at the rate of 60 fps for HDTV (1080x1920) frame.

Zaire ebolavirus a member of family Filoviridae is the cause of hemorrhagic fever. Due to lack of appropriate anti-viral or vaccine, this disease is very lethal. In this study we tried to find epitopes for superficial glycoprotein of Zaire ebolavirus (that have high antigenicity for MHC I, II and B cells) with use of in-silico methods and immunoinformatics approach. By use of CTLPred, SYFPEITHI and Propred web applications for MHC class I and SYFPEITHI and Propred1web applications for MHC class II we had been able to find epitopes (peptides) that have highest score. Also ElliPro, IgPred and Discotope web tools had been performed to predict B cells epitopes. The sequence "SRFTPQFLL" and "IFFLYDRLAS" were selected to be epitopes for MHCs molecules. The region 255 to 310 was selected for B cell epitope. It was expected these peptides could be stimulated immune response and used for designing multi-peptide vaccine against ZEV but these results should be reliable with experimental analysis.

Histogram of oriented gradients (HOG) is considered as the most promising algorithm in human detection, however its complexity and intensive computational load is an issue for real-time detection in embedded systems. This paper presents a hardware accelerator for HOG feature extractor to fulfill the requirements of real-time pedestrian detection in driver assistance systems. Parallel and deep pipelined hardware architecture with special defined memory access pattern is employed to improve the throughput while maintaining the accuracy of the original algorithm reasonably high. Adoption of efficient memory access pattern, which provides simultaneous access to the required memory area for different functional blocks, avoids repetitive calculation at different stages of computation, resulting in both higher throughput and lower power. It does not impose any further resource requirements with regard to memory utilization. Our presented hardware accelerator is capable of extracting HOG features for 60 fps (frame per second) of HDTV (1080x1920) frame and could be employed with several instances of support vector machine (SVM) classifier in order to provide multiple object detection.