Demo Data from VLDB 2026 / reviewers in the wild / expert
Ji-Heng Wu
dblp:153/0596
· DBLP profile ↗
1ranked-venue papers
0as first author
0since 2021 · last 2014
—ORCID · none
Domains — the database's venue-derived domains; a paper can count in several
Systems, architecture and hardware · 1
Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.
| Computer architecture, parallel and distributed computing, and storage systems
1 paper |
Electronic design automation · 83% Energy-efficient computing · 17% |
Topics — the 5 heaviest of 5, each with the papers that count most for it
| Topic | Weight | Papers | Last | Evidence papers |
|---|---|---|---|---|
Electronic design automation › physical design › floorplanning
fixed-outline floorplanning |
0.2 | 1 | 2014 | F-FM: Fixed-Outline Floorplanning Methodology for Mixed-Size Modules Considering Voltage-Island Constraint · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2014 |
Electronic design automation › physical design
floorplanning |
0.2 | 1 | 2014 | F-FM: Fixed-Outline Floorplanning Methodology for Mixed-Size Modules Considering Voltage-Island Constraint · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2014 |
Electronic design automation
physical design |
0.2 | 1 | 2014 | F-FM: Fixed-Outline Floorplanning Methodology for Mixed-Size Modules Considering Voltage-Island Constraint · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2014 |
Energy-efficient computing › low-power design
low-power VLSI design |
0.1 | 1 | 2014 | F-FM: Fixed-Outline Floorplanning Methodology for Mixed-Size Modules Considering Voltage-Island Constraint · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2014 |
Energy-efficient computing › voltage scaling
voltage islands |
0.1 | 1 | 2014 | F-FM: Fixed-Outline Floorplanning Methodology for Mixed-Size Modules Considering Voltage-Island Constraint · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2014 |
Methods — techniques the papers use, named apart from their topics
slicing tree representation · 0.2analytical placement · 0.2
| Year | Publication | Venue | Position |
|---|---|---|---|
| 2014 | F-FM: Fixed-Outline Floorplanning Methodology for Mixed-Size Modules Considering Voltage-Island ConstraintabstractThis paper presents a two-stage approach to handle fixed-outline floorplanning for mixed size modules, named F-FM. F-FM combines the advantages of the analytical approach and the slicing tree representation. Thus, it is not only suitable for handling fixed-outline floorplanning but also can be extended to handle other important issues in floorplanning such as routability or thermal effect in addition to wirelength. Recently, low power has become big challenges in very large-scale integration designs, which makes voltage-island driven floorplanning more important than ever. Although the problem has been discussed by previous works, no paper considers signal wirelength, powerplanning, and voltage drop at the same time under the fixed-outline constraint. Thus, this paper extends F-FM to handle this problem and consider these issues by properly dividing modules in a voltage domain into several islands. The experimental results show our approach obtains the best results in these problems. Jai-Ming Lin, Ji-Heng Wu |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. | 2 |