The heavy ion radiation performance of NCringFET with single and dual-k spacers using both the inner and outer drain arrangements are investigated using 3D TCAD simulations. DC performance parameters, including ON current (Ion), OFF current (Ioff), and Ion/Ioffratio, are obtained for all NCringFET structures. The behavior of NCringFET to heavy ion irradiation is analyzed, and the device’s susceptible area is identified via single-event transient analysis. It was discovered that the most susceptible area for an inner drain arrangement is the centre of the drain, whereas the most susceptible area for an outer drain arrangement is the spacer near the drain. The source region is the least susceptible area for both outer and inner drain arrangements. Also, the single-event transient performance of NCringFET-based Inverters using both outer and inner drain arrangements are examined. NCringFET with an inner drain arrangement exhibits improved performance in radiation-prone areas due to its reduced collected charge, making it a more suitable choice for applications requiring high reliability and radiation tolerance at both the device level and circuit level.

In this article, a well calibrated FDSOI ferroelectric (Fe)-FET/FeFET is gate-stacked with a charge trap nitride (CTN) for investigating memory and synaptic applications. The CTN is sandwiched between Fe and silicon channel of FeFET to obtain ferroelectric/oxide/nitride/oxide/semiconductor (FONOS) FET for improved memory and synaptic applications. This approach of using both Fe and CTN layers to improve memory and synaptic applications is labeled as hybrid approach. Since, both the Fe or CTN as a standalone gate-stack dielectric can give threshold-voltage ($V_{T}$) shift leading to hysteresis transfer characteristics with a program (PGM)/erase (ERS) schemes that predict a memory window (MW). The FeFET uses spontaneous polarization ($P_{S}$) to obtain memory operation which offer low power and area. The CTN uses highly mature and reliable charge-trapping-memory (CTM)-based e${}^{-} $/h+ trapping$\Leftrightarrow $de-trapping mechanism with PGM/ERS scheme to obtain MW that has high-$V_{T}$(HVT) and low-$V_{T}$(LVT) transfer characteristics. Hence, a combination of these leading to a FONOS FET architecture, which is investigated for improved memory properties like MW and retention followed by examining on synaptic attributes for realistic device training accuracy toward artificial neural networks (ANNs). From the investigations: 1) FONOS memory device has predicted improvement in MW with 2.65 V for 8-nm thick CTN layer and retention of Fe-electric field ($E_{\mathrm { Fe}}$) and charge density for$\approx 11$years and 2) synaptic device has shown an accuracy of 93% for MNIST digit dataset in ANNs. These predictions from the FONOS FET aimed at providing hybrid solutions to next-generation devices with extended applications in memory and neuromorphic applications with reliable device operation.