VLDB 2026 Research / reviewers in the wild / expert
Soumik Sinha
dblp:153/8042
· DBLP profile ↗
3ranked-venue papers
1as first author
2since 2021 · last 2023
0000-0002-5774-6634ORCID · corroborated
Domains — the database's venue-derived domains; a paper can count in several
Artificial intelligence and machine learning · 1Systems, architecture and hardware · 1 · 1 first-author · 1 since 2021Computer networks · 1 · 1 since 2021
Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.
| Network and information security
1 paper |
Cryptographic primitives and cryptanalysis · 100% | |
| Computer architecture, parallel and distributed computing, and storage systems
1 paper |
Hardware accelerators and domain-specific architectures · 100% | |
| Artificial intelligence
1 paper |
Probabilistic and Bayesian machine learning · 50% Language models and text generation · 50% |
Topics — the 5 heaviest of 6, each with the papers that count most for it
| Topic | Weight | Papers | Last | Evidence papers |
|---|---|---|---|---|
Cryptographic primitives and cryptanalysis › homomorphic encryption
fully homomorphic encryption |
0.6 | 1 | 2022 | Exploring Bitslicing Architectures for Enabling FHE-Assisted Machine Learning · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2022 |
Cryptographic primitives and cryptanalysis
homomorphic encryption |
0.6 | 1 | 2022 | Exploring Bitslicing Architectures for Enabling FHE-Assisted Machine Learning · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2022 |
Hardware accelerators and domain-specific architectures
machine learning accelerator |
0.6 | 1 | 2022 | Exploring Bitslicing Architectures for Enabling FHE-Assisted Machine Learning · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2022 |
Natural language and speech › Language models and text generation › trustworthy language model
privacy-preserving inference |
0.2 | 1 | 2022 | Exploring Bitslicing Architectures for Enabling FHE-Assisted Machine Learning · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2022 |
Machine learning › Probabilistic and Bayesian machine learning
statistical inference |
0.2 | 1 | 2022 | Exploring Bitslicing Architectures for Enabling FHE-Assisted Machine Learning · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2022 |
Methods — techniques the papers use, named apart from their topics
quantization · 1.7data packing · 1.7bit-slicing · 1.1bitslicing · 0.6
| Year | Publication | Venue | Position |
|---|---|---|---|
| 2023 | MDAP: Module Dependency based Anomaly Prediction
Harsh Borse, Bikash Sahoo, Prateek Chanda, Soumik Sinha, Mainack Mondal, Bivas Mitra |
Comput. Commun. | 4 |
| 2022 | Exploring Bitslicing Architectures for Enabling FHE-Assisted Machine LearningabstractHomomorphic encryption (HE) is the ultimate tool for performing secure computations even in untrusted environments. Application of HE for deep learning (DL) inference is an active area of research, given the fact that DL models are often deployed in untrusted environments (e.g., third-party servers) yet inferring on private data. However, existing HE libraries [somewhat (SWHE), leveled (LHE) or fully homomorphic (FHE)] suffer from extensive computational and memory overhead. Few performance optimized high-speed homomorphic libraries are either suffering from certain approximation issues leading to decryption errors or proven to be insecure according to recent published attacks. In this article, we propose architectural tricks to achieve performance speedup for encrypted DL inference developed with exact HE schemes without any approximation or decryption error in homomorphic computations. The main idea is to apply quantization and suitable data packing in the form of bitslicing to reduce the costly noise handling operation, Bootstrapping while achieving a functionally correct and highly parallel DL pipeline with a moderate memory footprint. Experimental evaluation on the MNIST dataset shows a significant ( $37\times$ ) speedup over the nonbitsliced versions of the same architecture. Low memory bandwidths (700 MB) of our design pipelines further highlight their promise toward scaling over larger gamut of Edge-AI analytics use cases. Soumik Sinha, Sayandeep Saha, Manaar Alam, Varun Agarwal, Ayantika Chatterjee, Anoop Mishra, Deepak Khazanchi, Debdeep Mukhopadhyay |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. | 1 |
| 2014 | Top - K Query Retrieval of Combinations with Sum-of-Subsets Ranking
Subhashis Majumder, Biswajit Sanyal, Prosenjit Gupta, Soumik Sinha, Shiladitya Pande, Wing-Kai Hon |
COCOA | 4 |