Computer vision and machine learning algorithms operating under a strict power budget require an alternate computing paradigm. While bitstream computing (BC) satisfies these constraints, creating BC systems is difficult. To address the design challenges, we propose compiler extensions to B it SAD, a DSL for BC. Our work enables bit-level software emulation and automated generation of hierarchical hardware, discusses potential optimizations, and proposes compiler phases to implement those optimizations in a hardware-aware manner. Finally, we introduce population coding, a parallelization scheme for stochastic computing that decreases latency without sacrificing accuracy, and provide theoretical and experimental guarantees on its effectiveness.

Emerging neural hardware substrates, such as IBM's “TrueNorth” neurosynaptic system, can provide an appealing platform for deploying numerical algorithms. For example, a recurrent Hopfield neural network can be used to solve for the Moore-Penrose matrix inverse, which enables a broad class of linear optimizations to be solved efficiently, with very low energy cost. However, deploying numerical algorithms on hardware platforms that severely limit the range and precision of representation for numeric quantities can be quite challenging. This paper discusses these challenges and experimentally validates that generalized inverses can be correctly computed on such substrates. Specifically, we show that several real-time applications that require matrix inverse computations to solve systems of linear equations can be correctly implemented on hardware-constrained neural substrates. The Hopfield linear solver model is empirically validated on the IBM TrueNorth platform, and results show promising potential for deploying an accurate and energy-efficient generalized matrix inverse engine calculator, with compelling real-time applications including target tracking (object localization), optical flow, and inverse kinematics.

The mammalian visual system is uniquely capable of robustly recognizing objects in its field of view regardless of their orientation, scale, or position, while learning new objects from a small number of training examples and generalizing robustly to a broad class of visually similar objects. The cortical structures that implement the visual system have been successfully emulated in several biologically-inspired synthetic vision systems. Developmental evidence lends credence to the claim that visual cortical structures emerge during development, i.e. they self-organize, when exposed to training stimulus. This paper demonstrates that a set of simple developmental rules can govern the emergence of a self-learning variant of a map-seeking circuit (SL-MSC) in a simulated visual system. The SL-MSC is capable of the same visual tasks as the original hand-crafted MSC: object recognition independent of rotation, translation, and scaling, and the ability to identify and learn new objects. The SL-MSC learns invariant visual transformations by relying on temporal association in its visual field, and is able to group the transformations into independent layers. Experimental results show that the SL-MSC can generalize the rotation, translation, and scaling transformations learned for one object to new objects, leading to learning and recognition of new objects with very few training samples.

CORDIC (COordinate Rotational DIgital Computer) has gained momentum for decades because of its less hardware complexity in real time applications such as communication systems, signal and image processing. The main drawbacks of CORDIC algorithm are increased number of iterations, scale factor calculation and compensation. Researchers have worked to reduce the latency in terms of number of iterations and minimize the critical path with redundant arithmetic and fast adders. Some researchers have proposed algorithms to reduce the number of iterations to${\mbi{n}}/{\bf 2}$plus additional iterations including rotation and scale factor calculation and compensation for${\mbi{n}}$bit precision. However, to the knowledge of the authors, no further reduction of number of iterations has been addressed. In this context, the authors have proposed a new hybrid CORDIC algorithm which reduces the iteration to$({\bf 3}{\mbi{n}}/{\bf 8}) + {\bf 1}$for${\mbi{n}}$bit precision including the scale factor calculation and compensation. The proposed algorithm and its first order architecture have been compared with the existing low latency CORDIC algorithms in terms of iterations, hardware complexity and critical delay. The scope of this work is to present a novel hybrid CORDIC algorithm along with first order hardware architecture.