Redundant elements in memories have long been used to enhance the manufacturing yield of silicon devices. Although redundant elements allocated during manufacturing tests are fully tested, unallocated elements remain untested. To increase device reliability, allocation of unused redundant elements and in-field testing may become necessary throughout the lifecycle of a device. In other words, all redundant elements must be tested during manufacturing to prevent the allocation of a defective spare in the field. This paper presents a novel hardware architecture and manufacturing test flow required to systematically test all redundant row elements and preemptively identify defective ones. This solution ensures that only reliable unallocated spare elements remain available for in-system repair.

Adherence to the ISO 26262 standard requires periodic testing of embedded memories in automobiles, which must be completed within short time windows during normal vehicle operation. This testing must preserve memory contents post-test and integrate test logic seamlessly with system functionality, all while minimizing disruption to vehicle performance. This paper proposes a Memory Built-In Self-Test (MBIST) architecture that addresses these challenges by using a series of short test bursts. The architecture dynamically adjusts the length of each burst based on available memory idle time, ensuring efficient testing without interfering with critical system functions. Additionally, the architecture minimizes hardware overhead by reusing existing resources and introduces a direct access interface for tighter integration with system logic, further enhancing test efficiency and reducing latency.

An increasing number of embedded memory instances, despite lowering the power supply voltage and technology node size, leads to higher power dissipation during the memory test phase when manufacturing a System-on-Chip (SoC). Commonly used manual memory test scheduling techniques need to be replaced with more systematic approaches. The objective is to minimize the test time through concurrent memory testing, resulting in maximization of the dissipated power, but in the way the given power budget is not exceeded. The paper comprises two topics. Firstly, it presents a toolchain aimed at a thorough monitoring of the power dispersed by memory instances and associated Memory Built-In Self-Test (MBIST) instruments. Secondly, several algorithms are proposed that optimize the memory test scheduling for a commercial Design-for-Test (DFT) tool.

A tile based design methodology consists of developing design blocks that are inserted in design layouts by placing blocks next to each other, making a tile-to-tile connection by abutting corresponding physical signal lines at the border of the tile. Very large systems can be easily and rapidly developed by seamlessly integrating tile elements in the layout. Further, the ease of top-level integration underlines the advantages over a bottom-up approach. However, this tile-based approach is incompatible with traditional DFT tools, which were created to work in accordance with the bottom-up design methodology. This paper outlines some of the obstacles to overcome, to support a truly tile-based DFT methodology. We describe here a working solution for a large production design, underlining a successful implementation of a tile-based Memory Test methodology.

In the paper, two methods of ensuring high quality of the memory built-in self-test tools are presented. The described ideas illustrate general methods and are applicable to any commercial memory BIST tool. The first solution describes controller emulation in order to validate each step of the real controller's operations. The second approach presents a way to determine the test algorithms' fault coverage by means of the memory fault simulator. The experimental results show functional benefits and effectiveness of the proposed solutions.