Test costs for large industrial designs increase rapidly in recent years. On-chip test compression hardware has become a pragmatic technology to cut down the overall test costs by reducing the test data volume. Determining the input and output channel counts of test compression hardware that results in minimum test data volume is thus a critical issue. In this article, efficient methods to estimate test pattern counts for an extensive range of input/output counts are developed. These methods require only a small number of ATPG runs. The estimation results can then be utilized to determine the test data volume for each input/output configuration. The configuration with the estimated lowest test data volume thus can be determined. The pattern count results of each configuration for a design can also be used to determine the best suitable configuration when the design is to be embedded in an SoC system.

This paper presents the structural testing challenges for Intel's high-performance IA Cores and the novel ATPG solutions developed to overcome them. Intel's IA Cores employ a design structure which, poses unique testing challenges for industry-standard design-for-testing (DFT) tools. First, the prevalent use of both latches and flip-flops while employing a two-phase clocking scheme. Second, the structural-based patterns reuse the functional clock network, hence keeping the performance and power profile similar to that of a functional test. Such design properties introduce unique Automatic-Test-Pattern-Generation (ATPG) challenges. The paper will introduce the innovative enhancements to the Design Rule Checks (DRCs), developed to handle these unique designs.

As the complexity of industrial integrated circuits continue to increase rapidly, test data compression has now become a de facto technology for large designs to reduce the overall test cost. During the design for test (DFT) planning, it is critical to understand the impact of using different numbers of input/output test channels on test coverage, test cycles, and test data volume. In this paper, two approaches to predict the test pattern counts and test data volumes with different input channel counts are presented, one with the compression tool able to generate channel-scaling patterns and the other without this capability. The results can be used to determine the scan test configuration that results in the smallest or near smallest test data volume. Experiments on industrial circuits show that the average error rates of pattern count prediction for most circuits are less than 10% for both approaches. The error rates of the predicted smallest data volumes are all less than 3.5%. The total ATPG run time can be reduced by a factor of more than 10X compared to the currently used trial-and-error approach.

Logic built-in self-test (LBIST) is now increasingly used with on-chip test compression as a complementary solution for in-system test, where high quality, low power, low silicon area, and most importantly short test application time are key factors affecting ICs targeted for safety-critical systems. Test points, common in LBIST-ready designs, can help to reduce test time and the overall silicon overhead so that one can get desired test coverage with the minimal number of patterns. Typically, LBIST test points are dysfunctional when enabled in an ATPG-based test compression mode. Similarly, test points used to reduce ATPG pattern counts (PCs) cannot guarantee desired random testability. In this paper, we present a hybrid test point technology designed to reduce deterministic PCs and to improve fault detection likelihood by means of the same minimal set of test points. The hybrid test points are subsequently deployed in a scan-based LBIST scheme addressing stringent test requirements of certain application domains such as the automotive electronics market. These requirements, largely driven by safety standards, are met by significantly reducing test application time while preserving the high fault coverage. The new scheme is a combination of pseudorandom test patterns delivered in a test-per-clock fashion through conventional scan chains and per-cycle-driven hybrid observation test points that capture faulty effects every shift cycle into dedicated scan chains. Their content is gradually shifted into a compactor shared with the remaining chains that deliver responses once a test pattern has been shifted-in. Experimental results obtained for industrial designs confirm feasibility of the new schemes, and they are reported herein.

This is the extended summary of the PhD thesis on new test point insertion techniques. The thesis provides a comprehensive study of innovative DFT schemes going far beyond traditional logic BIST-based applications of test points. The proposed methods visibly decrease pattern counts, reduce test generation and test application times, and increase test coverage by means of algorithms capable of identifying and resolving conflicts between circuit's internal signals. In particular, it is shown that new test points provide, on the average, 2×-3× increase in test compression for stuck-at, transition and cell-aware patterns. Furthermore, it is demonstrated that test-point-centric DFT logic can be successfully used to lock a circuit or hide its functionality. As a result, this approach improves the overall hardware security against reverse engineering, IC cloning, and IP theft.

Growing reverse-engineering attempts to steal or violate a design intellectual property (IP), or to identify the device technology in order to counterfeit integrated circuits (ICs), raise serious concerns in the IC design community. As the information derived from these practices can be used in a number of malicious ways, various active techniques have been proposed and deployed to protect IP, of which logic locking is a vital part. It allows inserting certain gates in a circuit's data path to lock outputs to fixed logic values, if a wrong unlocking key is applied. This paper demonstrates that test points-industry-proven design-for-test technology used primarily to enhance the overall design testability-can also be reused in the mission mode to lock the circuit, and thus to improve the hardware security against IP piracy. In particular, it is shown that test points can facilitate the hiding of design functionality from adversaries. As a result, not only is the overall design testability improved, but also effective protection against piracy through unauthorized excess production and other forms of IP theft is ensured. Experimental results on industrial designs with test points demonstrate that the proposed scheme is effective in achieving a desired degree of hardware obfuscation.

This paper presents a novel low-area scan-based logic built-in self-test (LBIST) scheme that addresses stringent test requirements of certain application domains such as the fast-growing automotive electronics market. These requirements, largely driven by safety standards, are met by significantly reducing test application time while preserving the high fault coverage of conventional BIST schemes. Alternatively, one may consider applying a much larger number of vectors within the same time interval. Although the new scheme may resemble traditional BIST logic, it is a combination of pseudorandom test patterns delivered in a test-per-clock fashion through conventional scan chains and per-cycle-driven hybrid test points that creates this new synergistic LBIST paradigm. The hybrid observation points, inserted at the most suitable locations, capture faulty effects every shift cycle into dedicated flip-flops that form separate scan chains. Their content is gradually shifted into a compactor, which is shared with the remaining scan chains that still deliver test responses captured once the entire test pattern has been shifted-in. Experimental results obtained for industrial designs illustrate feasibility of the proposed BIST scheme in terms of test time, test coverage, and area overhead, and they are reported herein.

There is mounting evidence that automatic test pattern generation tools capable of producing tests with high coverage of defects occurring in the large semiconductor nanometer designs unprecedentedly inflate test sets and test application times. A design-for-test technique presented in this paper aims at reducing deterministic pattern counts and test data volume through the insertion of conflict-aware test points. This methodology identifies and resolves conflicts across internal signals allowing test generation to increase the number of faults targeted by a single pattern. This is complemented by a method to minimize silicon area needed to implement conflict-aware test points. The proposed approach takes advantage of the conflict analysis and reuses functional flip-flops as drivers of control points. Experimental results on industrial designs with on-chip test compression demonstrate that the proposed test points are effective in achieving, on average, an additional factor of 2×-4× compression for stuck-at and transition patterns over the best up-to-date results provided by the embedded deterministic test (EDT)-based regular compression.

Recent reverse-engineering attempts to steal a competitive design intellectual property (IP) or to identify the device technology in order to counterfeit integrated circuits (ICs) have raised serious concerns in the IC design community. This paper demonstrates that test points - industry-proven design-for-test technology used to enhance the overall design testability - can also be deployed in the mission mode to obfuscate the circuit's structure, and thus to improve the hardware security against reverse engineering, IC cloning, and IP theft. In particular, it is shown how test points can facilitate the hiding of design functionality from adversaries. As a result, not only the overall design testability is improved, but also effective protection against reverse engineering and other forms of attacks is ensured.

Logic built-in self-test (LBIST), originally introduced for board, system, and in-field tests, is now being increasingly used with on-chip test compression. This hybrid approach allows LBIST to become a complementary solution for in-system test, where high quality, low power, low silicon area, and most importantly short test application time are key factors affecting ICs that are targeted for safety-critical and automotive systems. Test points are common in BIST-ready designs where they play a key role in reducing both test application time given a test coverage goal and the overall silicon overhead so that one can get a desired coverage with the minimal number of patterns. Unfortunately, these test points are typically dysfunctional when enabled in an ATPG-based test compression mode. Similarly, test points used to reduce ATPG-based test pattern counts cannot guarantee desired random testability. Incompatibility of both types of test points has motivated research presented in this paper. We present a novel hybrid test point technology designed to both reduce deterministic pattern counts and improve fault detection likelihood by means of the same minimal set of test points. Experimental results obtained for large industrial designs illustrate feasibility of the proposed hybrid test points and are reported herein.

This paper presents a new method to design digital circuits for low pattern counts, one of the key factors shaping cost-effective VLSI test schemes. The method identifies the largest conflicts between internal signals that prevent efficient test compaction in ATPG. These locations are modified by inserting conflict-reducing test points (CRTP) to significantly reduce the ATPG-produced pattern counts. Experimental results obtained for large industrial designs with on-chip test compression demonstrate, on average, 3x -- 4x reduction in stuck-at and transition patterns and 3x shorter ATPG times.

The introduction of FinFET technology has accelerated the adoption of patterns that target cell internal defects such as cell-aware tests. Even though cell-aware tests can replace stuck-at and transition patterns from the screening point of view, we have to address the increase in test data volume. This combined with the growing gate counts enabled by new technology nodes is driving the need for even greater compression levels. In this paper, we present a novel test points technology designed to reduce deterministic pattern counts for cell-aware tests. The technology is based on identification and resolution of conflicts across internal signals allowing ATPG to significantly increase the number of faults targeted by a single pattern. Experimental results on a number of industrial designs with test compression demonstrate that the proposed test points are effective in achieving, on average, a 3×–4× multiplicative increase in compression for 1-cycle and 2-cycle cell-aware patterns.

In the paper, two methods of ensuring high quality of the memory built-in self-test tools are presented. The described ideas illustrate general methods and are applicable to any commercial memory BIST tool. The first solution describes controller emulation in order to validate each step of the real controller's operations. The second approach presents a way to determine the test algorithms' fault coverage by means of the memory fault simulator. The experimental results show functional benefits and effectiveness of the proposed solutions.