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Eri Rubin

dblp:155/8202 · DBLP profile ↗
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2ranked-venue papers
1as first author
0since 2021 · last 2015
—ORCID · none

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 2 · 1 first-author

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
2 papers
GPUs and heterogeneous computing · 44% Memory systems · 27% Parallel and multicore computing · 23%

Topics — the 4 heaviest of 5, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Memory systems
memory access patterns
0.322015
MAPS: Optimizing Massively Parallel Applications Using Device-Level Memory Abstraction · ACM Trans. Archit. Code Optim. 2014
Memory access patterns: the missing piece of the multi-GPU puzzle · SC 2015
GPUs and heterogeneous computing
multi-GPU computing
0.212015
Memory access patterns: the missing piece of the multi-GPU puzzle · SC 2015
Parallel and multicore computing
task partitioning
0.212015
Memory access patterns: the missing piece of the multi-GPU puzzle · SC 2015
GPUs and heterogeneous computing
GPU programming
0.212014
MAPS: Optimizing Massively Parallel Applications Using Device-Level Memory Abstraction · ACM Trans. Archit. Code Optim. 2014

Methods — techniques the papers use, named apart from their topics

on-device containers · 0.2memory abstraction · 0.2iterators · 0.2
YearPublicationVenuePosition
2015 Memory access patterns: the missing piece of the multi-GPU puzzle
abstract
With the increased popularity of multi-GPU nodes in modern HPC clusters, it is imperative to develop matching programming paradigms for their efficient utilization. In order to take advantage of the local GPUs and the low-latency high-throughput interconnects that link them, programmers need to meticulously adapt parallel applications with respect to load balancing, boundary conditions and device synchronization. This paper presents MAPS-Multi, an automatic multi-GPU partitioning framework that distributes the workload based on the underlying memory access patterns. The framework consists of host- and device-level APIs that allow programs to efficiently run on a variety of GPU and multi-GPU architectures. The framework implements several layers of code optimization, device abstraction, and automatic inference of inter-GPU memory exchanges. The paper demonstrates that the performance of MAPS-Multi achieves near-linear scaling on fundamental computational operations, as well as real-world applications in deep learning and multivariate analysis.
Tal Ben-Nun, Ely Levy, Amnon Barak, Eri Rubin
SC4
2014 MAPS: Optimizing Massively Parallel Applications Using Device-Level Memory Abstraction
abstract
GPUs play an increasingly important role in high-performance computing. While developing naive code is straightforward, optimizing massively parallel applications requires deep understanding of the underlying architecture. The developer must struggle with complex index calculations and manual memory transfers. This article classifies memory access patterns used in most parallel algorithms, based on Berkeley’s Parallel “Dwarfs.” It then proposes the MAPS framework, a device-level memory abstraction that facilitates memory access on GPUs, alleviating complex indexing using on-device containers and iterators. This article presents an implementation of MAPS and shows that its performance is comparable to carefully optimized implementations of real-world applications.
Eri Rubin, Ely Levy, Amnon Barak, Tal Ben-Nun
ACM Trans. Archit. Code Optim.1