This work presents a ring oscillator (RO)-based low-jitter injection-locked clock and data recovery (ILCDR) with a pattern-dependent pulse filtering (PDPF) technique. The conventional ILCDR has a drawback that data jitter is transferred to the recovered clock. To reduce jitter, the PDPF technique is employed to filter out the injection pulses occurring in data patterns that cause high data-dependent jitter (DDJ). Adopting the PDPF technique with an injection timing control loop, the ILCDR optimizes injection timing and maximizes timing margin. Fabricated in a 28-nm CMOS technology, the proposed ILCDR occupies an active area of 0.03 mm2and consumes 13.6 mW at 10 Gb/s. The measured jitter tolerance (JTOL) is 1 UIppat 35 MHz with a bit error rate (BER) of$10^{-12}$.

This paper presents a referenceless baud-rate clock and data recovery (CDR) circuit with an integrated pattern decoding technique for fast frequency acquisition. The proposed CDR achieves baud-rate frequency acquisition without edge sampling clock phase by utilizing an integrator circuit. The proposed integrated pattern decoding technique divides 6-bit sequential patterns into 5 pattern groups. The patterns of each pattern group are detected from the specific frequency offsets. By applying larger weights to the pattern groups including the patterns detected at the higher frequency offset, the proposed referenceless CDR achieves fast frequency acquisition. Fabricated in a 28-nm CMOS technology, the CDR prototype occupies 0.039 mm2and consumes 30.77 mW at 30 Gb/s. From various initial clock frequency, the proposed CDR achieves a capture range from 16 Gb/s to 30 Gb/s. Thanks to the fast frequency acquisition ability of the proposed integrated pattern decoding technique, the worst frequency acquisition time at the data rate of 30 Gb/s is$3.7~\mu $s. The CDR achieves a bit error rate (BER) of less than$10^{-12}$and an energy efficiency of 1.03 pJ/b.

This paper presents a single-ended three-level pulse amplitude modulation (PAM-3) transceiver employing crosstalk cancellation (XTC) techniques for next-generation memory interfaces. The proposed 3-ternery-to-4-ternery (3T4T) coding and feed-forward equalizer (FFE)-based XTC facilitate adopting PAM-3 signaling while maximizing channel density in the high-density memory interfaces. The proposed 3T4T coding reduces data-dependent jitter (DDJ) induced by inter-symbol interference (ISI) and mitigates the effect of crosstalk and maximum simultaneous noise (SSN) by half. The prototype transceiver is designed and fabricated in 28-nm CMOS process with a high-density on-chip channel which channel pitch is$1.0~\mu $m, obtaining an edge bandwidth density of 18 Tb/s/mm. The proposed PAM-3 transceiver achieves a crosstalk-induced jitter (CIJ) reduction of 0.846 unit interval (UI) with 90% CIJ reduction ratio at 18 Gb/s, and energy efficiencies of 1.103 pJ/bit and 0.764 pJ/bit for the transmitter and receiver, respectively. A bit error rate (BER) less than$10^{-12}$is verified with an eye margin of 0.40 UI.

This paper analyzes an effect of inter-wire skew on signal integrity in a multi-channel system and proposes circuit techniques to enhance signal integrity by using a spatially correlated coded signaling (SCCS). Through the in-depth analysis, the paper investigates a relation between skew and insertion loss (IL), and highlights an importance of wide-range inter-wire de-skewing (IWD). The proposed phase interpolator (PI)-based IWD technique adjusts the transition edges of receiver inputs to minimize skew caused by mismatch components, which increases timing jitter. The transceiver employs pseudo-differential signaling to verify the effect of the IWD in SCCS. The transmitter integrates a feed-forward equalizer (FFE) with a latch-based re-timer and a PI for each channel. Additionally, a 3-tap FFE at the transmitter and a continuous-time linear equalizer (CTLE) at the receiver are incorporated to compensate for channel ISI. Fabricated in 40-nm CMOS technology, the proposed 8-channel transceiver achieves an aggregate throughput of 112 Gb/s with a bit error rate (BER) below$10^{\mathbf {-12}}$. The transceiver occupies 0.382 mm2while achieving energy efficiencies of 0.77 pJ/bit/ch for the transmitter and 1.45 pJ/bit/ch for the receiver.

A compact power-on-reset (POR) circuit with a configurable brown-out reset (BOR) function is presented. An integrated voltage reference (VR) circuit provides a constant bias voltage that facilitates voltage-triggered POR/BOR operation, reliably preventing POR signal generation when the ramping supply voltage (${V} _{\text {DD}}$) level is too low. Moreover, the proposed POR circuit features a fast, configurable POR/BOR operation owing to an inverter-based trip point detector (TPD), which triggers the reset signal with a programmable trip point. The prototype POR circuit achieves a POR level higher than 752 mV with a maximum POR delay of$16.4~\mu $s at a 0.8–1.2-V${V} _{\text {DD}}$, supporting a wide range of supply ramping time from$1~\mu $s to 1 s. In addition, the prototype detects brown-out events with a supply drop of 0.1–0.4 V, generating the BOR signal. Designed using a 28-nm CMOS process, the prototype has a compact active area of$995.3~\mu $m2and a quiescent current of 162–974 nA at a 1-V${V} _{\text {DD}}$.

This brief presents an energy-efficient transceiver supporting a 10-Gb/s/lane display link interface between the application processor (AP) integrated circuits (IC) and timing controller (TCON)-embedded source driver IC for mobile applications. An embedded clocking scheme is adopted to save clock distribution power, which also reduces the required number of off-chip I/O channels. A transmitter (TX) sends 20-Gb/s aggregate data through two differential data lanes, and a receiver recovers a 5-GHz half-rate clock. The TX employs a latch-less serializer using divided clocks in a staggered phase, achieving energy efficiency of 0.43 pJ/b/lane. In the RX, a hybrid clock and data recovery (CDR) tracks a half-data rate with a digital loop filter (DLF) and subsequently locks the frequency and phase with an analog loop filter (ALF). By deactivating the DLF and edge deserializer once a coarse frequency lock is acquired, the RX achieves an energy efficiency of 0.53 pJ/b/lane. The prototype transceiver, fabricated using a 28-nm CMOS technology, occupies an active area of 0.196 mm2 and achieves an energy efficiency of 1.23 pJ/b/lane, including a charge-pump phase-locked loop (CP-PLL) with clock distribution.

We present an LC-based hybrid sub-sampling phase-locked loop (PLL). A novel tri-state integral path is applied to reduce the loop filter (LF) area and eliminate ripples on the control signals. The effectiveness of the proposed technique is compared with type-II hybrid PLL and PLL using delta-sigma modulator. The 24.6-29.6GHz PLL instance implemented in 28-nm planar process achieves RMS jitter of 44fs and -254.8dB FOM and consumes power of 17mW from a 0.9/0.95V supply.

A change from a non-return-to-zero (NRZ) signaling to a four-level pulse amplitude modulation (PAM-4) signaling causes various challenges in clock and data recovery (CDR) designs as well as analog-front-end (AFE) designs. A PAM-4 CDR with a 2x-oversampling phase detector (PD) has an issue of increased pattern-dependent jitter due to asymmetric transitions. This work investigates a similar problem in a baud-rate CDR by analyzing the PD characteristics. In the PAM-4 baud-rate sampling, the transitions are classified into two types: full-swing transitions and non-full-swing transitions. Since utilizing the non-full-swing transitions can affect the jitter tracking ability, careful consideration of decisions using these transitions is necessary to optimize the jitter performance. To address this issue, we propose an asymmetric-weighted PD that minimizes pattern-dependent jitter and maximizes a transition density by utilizing both the full-swing transitions and the non-full-swing transitions. Using a pseudo-linear analysis, the proposed PD achieves improved jitter performance compared to the conventional PD. Fabricated in 28-nm CMOS process, a prototype PAM-4 receiver with the proposed CDR is demonstrated at 40 Gb/s. The CDR achieves a bit error rate (BER) less than 10$^{-9}$and an energy efficiency of 1.65 pJ/b.

This paper presents a 50-Gb/s receiver (RX) with an adaptive phase-shifting (APS) phase detector (PD) for four-level pulse amplitude modulation (PAM-4) clock and data recovery (CDR). The APS PD adopts a$\beta $detector to achieve a unique locking point that resolves the dead-zone problem caused by the combination of the conventional baud-rate PD and adaptive decision feedback equalizer (DFE). The APS CDR is configured with a sign-sign minimum mean squared error (SS-MMSE) PD and an addition of a digital coefficient which is adaptively controlled through the$\beta $detector by detecting pre-cursor inter-symbol interference (ISI) dependency of 1-level transitions. Therefore, the proposed CDR does not rely on external coefficients. Furthermore, adaptive programmable gain amplifiers (PGAs) and DFE are implemented with the APS CDR to compensate the pre and post-cursor ISIs, and main-cursor level. Since the adaptive equalizers and the APS CDR share the error samplers, no additional analog hardware is required. Fabricated in 28-nm CMOS technology, a prototype PAM-4 RX operates at 50 Gb/s and occupies an active area of 0.16 mm$^{2}$. The RX tested over a 25.3-dB loss channel achieves a bit error rate (BER) of less than 10$^{-12}$and energy efficiency of 2.52 pJ/b.

A 10 Gb/s PLL-based forwarded clock receiver is implemented in 65-nm CMOS technology. The proposed architecture uses a hybrid PLL-based deskew which is combined with a PLL and a DLL. The PLL provides jitter filtering and the DLL performs deskewing by shifting the divided clocks. Since the operating frequency of the DLL is low, the power consumption of the DLL can be reduced. The measurement results show that the rms jitter of the recovered clock is only 576.7 fs which is quite low for a ring-oscillator-based PLL. The receiver chip occupies an active area of 0.0136 mm2and consumes 22.1 mW at the data rate of 10 Gb/s.