This paper presents an analysis of the application of an intentionally mismatched capacitive Digital-to-Analog Converter (CDAC) to improve the area efficiency and accuracy of successive-approximation register (SAR) analog-to-digital converters. The proposed SAR ADC architecture, the redundant capacitor-saver SAR ADC, utilizes 1-bit redundancy with intentional mismatch to estimate an additional resolution bit. This redundancy bit not only enhances noise tolerance but also achieves higher resolution through area- and energy-efficient computations, without requiring the addition of non-ideal, area-consuming, and energy-intensive capacitors to the CDAC block of the conventional SAR ADC. Simulations were conducted using Cadence TSMC 130nm CMOS technology and MATLAB software for conventional, redundant, and redundant capacitor-saver SAR ADCs, demonstrating 3 dB and 2 dB improvements in SNDR and SFDR, respectively, when using the capacitor-saver DAC architecture.

We present a framework for the development of closed-loop neurostimulators that can deliver patient-optimized and temporally-adaptive stimulation pulses for epileptic seizure control. While many studies have targeted patient-specific seizure detection, little attention has been given to tailoring stimulation parameters for individual patients. This work prioritizes patient-specific stimulation optimization, assuming the seizure has already been detected. The proposed method employs a model predictive controller (MPC) that can rapidly converge to an optimal set of stimulation parameters for a specific patient thanks to being pre-trained with a neural mass model (NMM) that is fine-tuned to the patient's pre-recorded data. The development and patientspecific customization of the NMM are presented, showing its ability to generate synthetic intracranial electroencephalography (iEEG) with consistently-high spectral correlation to real prerecorded iEEG, for both normal and seizure periods (with a statistically-significant number of samples). We also showcase how these patient-customized NMMs are used along with the MPC to optimize the stimulation parameters for seizure control. Examples from both sub-optimal and optimal stimulation therapies are presented, as well as how the parameter space is navigated efficiently by leveraging historical data, leading to convergence towards an optimal point with minimal iterations.

A neuromorphic spiking convolutional neural network (SCNN) is presented for cross-patient seizure detection using multi-modal features from multi-channel electroencephalogram (EEG) data. A mixture of spectral, temporal, and spatial features is employed for building robustness against domain-specific noise/artifacts, hence boosting detection sensitivity and specificity. The feature set is converted to temporally-coded spikes before being fed to the SCNN classifier. Thanks to the asynchronous spike-based multiplier-less operation, the SCNN significantly reduces the classification computational cost without sacrificing accuracy. The developed algorithm was validated on a publicly available dataset and an average sensitivity of 83.02%, a specificity of 86.31%, and a false positive rate of 0.69/hr were achieved for cross-patient seizure detection. Our results show that a 1-bit Integer-Net leads to less than 2% drop in sensitivity compared with a 32-bit real-value resolution CNN model while offering more than 27× improvement in memory efficiency. The SCNN achieves an estimated energy efficiency of$1.28\mu\mathrm{J}$/classification, which translates into a 98.6% improvement compared to a conventional CNN implementation with the same accuracy.

Design, implementation, and post-layout validation of a DC-coupled chopper-stabilized continuous-time $\triangle\Sigma$-based ADC-direct artifact-tolerant neural recording circuit is presented. The architecture employs a dual fine-coarse first-order $\triangle\Sigma$ modulator to simultaneously record $\mu$V-level neural signals in the presence of DC offsets and differential artifacts up to ±140mV. The input transconductance stage (capable of handling rail-to-rail CM input with200G$\Omega$ input impedance for the entire frequency band of interest (DC-5kHz). Chopper stabilization is also conducted at the input to minimize flicker noise (Integrated IRN: 1.22$\mu V_{rms}$). Our transient simulation results show the circuit’s capability in differential artifact recovery under 200$\mu$s. Thanks to avoiding multi-bit capacitive/resistive DACs and using the same loop filter blocks for both neural recording and artifact compensation, a channel area of 0.035m$\text{m}^{2}$ is achieved, which is largely dominated by process-scalable digital blocks. The entire recording circuit consumes 5.4$\mu$W and yields an effective dynamic range of 50+40.9dB for neural signals and artifacts. The circuit’s performance comparison to the state of the art is also presented. keywords: Neural recording, stimulation artifact, high DR, ADC direct architecture, DC coupled input, artifact tolerant.

The development, analysis, and experimental validation of an energy storage algorithmic scheme for performance optimization of resonant inductive power receivers are presented. Motivated by the crucial role of efficient energy storage in the next generation of brain-implantable devices, we introduce an energy management strategy in the design of wireless powering links, in which, the key performance measure is the energy stored during a limited time interval rather than the average energy delivered to the load. The presented strategy is proven analytically to yield the theoretically-maximum energy storage efficiency over a pre-determined period of time. Additionally, thanks to the algorithm's closed-form solution, the optimization can be done in real time, offering the potential for a solution that is adaptive to any variations in physical (e.g., coil separation, Rx rotation, etc.) and/or electrical (e.g., Q-factor, media conductivity, etc.) properties of the link, conditional to a low-power circuit implementation for its evaluation. The efficacy and precision of the solution obtained from the presented analytical model is confirmed with CAD-based simulation results, and later validated using experimental measurements. Our experimental results for two links with different characteristics (resonance frequency, coils size and separation, etc.) show a 52.5% and 67.5% improvement in overall energy storage efficiency compared to the standard CM receiver design in which resonance-to-charging switching is performed when the receiver's LC tank energy accumulation starts to saturate. This is while the presented method does not require any calibration and is designed to be employed by any generic current-mode receiver.

An 8-channel integrated circuit for motion-artifact-resilient EEG recording is reported. The presented IC employs a novel mixed-signal channel architecture capable of real-time motion artifacts detection and removal in the analog domain, making it needless of an ADC and/or digital signal processing. The channel's detailed design analysis, system-level architecture, circuit-level implementation, and experimental characterization results are presented. The microchip is sized 12 mm2and is fabricated in a 130nm CMOS technology. Our measurement results show a voltage gain of 48.3dB, a bandwidth of up to 300Hz, rail-to-rail input DC offset tolerance and 41.5dB artifact suppression while consuming 55μW per channel.

Design, VLSI implementation, and validation results of a patient-specific RBF-SVM algorithm for monitoring and closed-loop control of high blood pressure in patients with resistant hypertension are presented. To ensure minimal invasiveness, the algorithm only uses a single-channel ECG signal as its sensory input. The feature extraction and classification are designed and optimized to be inexpensive both in terms of computational resources and energy consumption, enabling algorithm's integration within the highly-restricted size and power budget of an implantable device. The VLSI implementation using a hardware description language is also presented. Our results show that the implementation of the algorithm on a miniature Microsemi AGL250 low-power FPGA requires 493 logic elements, 7.4kbit of memory, consumes 19.98μW dynamic power (clocked at 1MHz), and yields a classification latency of 180μs. The algorithm classification performance is evaluated on a two different pre-recorded labeled ECG database with 14 healthy and 14 sick subjects and shows an average sensitivity, specificity, and accuracy of 89%, 98%, and 94.5%, respectively.

The design, optimization, and validation results of a patient-specific seizure detection algorithm are presented. The algorithm employs both mono-variate (spectral energy) and bivariate (narrow-band phase synchrony) features. The computational complexity of both feature extraction and brain state classification is optimized to enable the algorithms integration into a low-power implantable/wearable microprocessor. The patient specificity of the algorithm includes (a) the nonlinear RBF-SVM classifier's hyperplane characteristics, (b) band selection for phase extraction, and (c) channel selection (dimensionality reduction) for spectral energy extraction. The algorithms performance is validated on pre-recorded EEG data from 23 patients (969 hours, 198 seizures in total) and shows a seizure detection sensitivity and specificity of 96.87% and 99.95%, respectively. A comparison to the state of the art in terms of various design and performance parameters is presented.

An ADC-direct energy-efficient temperature sensor with a novel multi-range BJT-based transducer design is presented. Thanks to the novel transducer design, the proposed NPN-based sensor does not require any analog-domain pre-ADC signal conditioning. Through bias current control, the sensing range can be adjusted for different applications. Our simulation results show a 2.67 × improvement in ADC dynamic range utilization for the military (-55° C to 125° C) and 3.8 × improvement for the medical (0°C to 100° C) temperature ranges, respectively. An Incremental ΔΣ-based readout circuitry for the proposed sensor has also been implemented and the circuit- and system-level simulation results are presented. The entire design draws 2.6μA from a 1.2V supply voltage to yield a resolution of 0.01° for a conversion time of 100ms, achieving a resolution FoM of 3.12pJ°C2.

An 8-channel wearable wireless device for surface EEG monitoring is presented. The entire multi-channel recording, quantization, and motion artifact removal is implemented on a 4-layer polyimide flexible substrate. The recording electrodes and active shielding are also integrated on the same substrate, yielding the smallest form factor compared to the state of the art. Thanks to the dry non-contact electrodes, the system is quickly mountable with minimal assistance required, making it an ideal frontal and temporal-lobe EEG monitoring device in emergency departments. The flexible main board is connected to a rechargeable battery on one end and to a 13×17mm2rigid board on the other end. The mini rigid board hosts a low-power programmable FPGA and a BLE 5.0 transceiver, which add diagnostic capability and wireless operation features to the device, respectively. The device performance in terms of voltage gain (260 V/V), bandwidth (DC-700 Hz), input-referred noise, motion artifact removal, and wireless communication throughput (up to 1Mbps) is experimentally validated and the overall power consumption is measured to be 27mW. The entire wearable solution with the battery weight 9.2 grams.

Design, VLSI implementation, and experimental validation of a resource-optimized machine-learning algorithm for epilepsy seizure detection is presented. The algorithm uses only signals from the frontal and the front-temporal lobes EEG electrodes while yielding a seizure detection performance competitive to the standard full EEG systems. The experimental validations prove the possibility of conducting accurate seizure detection using quickly-mountable dry-electrode headsets without the need for uncomfortable/painful through-hair electrodes or adhesive material. The compact VLSI implementation of the algorithm is also presented and resource optimization techniques are discussed. The optimized implementation is uploaded on an Actel Igloo AGL250 low-power FPGA, requires 1237 logic elements, consumes 110μW dynamic power, and yields a detection latency of 10.2μs. The measurement results from the FPGA implementation on data from 23 patients (198 seizures in total) shows a seizure detection sensitivity and specificity of 92.5% and 80.1%, respectively.

An inductively-powered implantable microsystem for monitoring and treatment of intractable epilepsy is presented. The miniaturized system is comprised of two mini-boards and a power receiver coil. The first board hosts a 24-channel neurostimulator SoC developed in a 0.13μm CMOS technology and performs neural recording, electrical stimulation and onchip digital signal processing. The second board communicates recorded brain signals as well as signal processing results wirelessly, and generates different supply and bias voltages for the neurostimulator SoC and other external components. The multi-layer flexible coil receives inductively-transmitted power and sends it to the second board for power management. The system is sized at 2 × 2 × 0.7 cm3, weighs 6 grams, and is validated in control of chronic seizures in vivo in freely-moving rats.

A wearable-optimized implementation of a sleep stage classification algorithm that has low detection latency, high detection accuracy and low resource consumption is developed and successfully implemented on a low-power FPGA microsystem for closed-loop electrical brain stimulation. This implementation uses EEG and EMG signals as inputs and classifies stages of sleep. By structurally merging multichannel FIR and window averaging filters into one reconfigurable, multipurpose filter, the new implementation maintains a sleep detection accuracy of 79.7%, a REM detection sensitivity of 98.2%, a REM detection specificity of 89.2% and a detection latency of 0.982 ms, while consuming 6.8 times fewer logic elements and 96.28% less power compared with the current state of the art implementation. With its high performance and low resource usage, this implementation enables a low-power wearable microsystem to perform neural recording, real-time REM sleep stage detection, and closed-loop responsive brain stimulation as a tool to study the mechanisms of neurodegenerative diseases.

This paper discusses general tradeoffs between wireless communication and computation in closed-loop implantable medical devices for neurological applications. Closed-loop devices enable neural monitoring, automated diagnostics and treatment of neurological disorders. Several topologies for the loop a re discussed, including within the implant, as well as implemented with a wearable, handheld or stationary processor. Common wireless communication data rate and range requirements and algorithmic computational requirements are summarized. As a case study, a 0.13 μm CMOS neurostimulator SoC for closed-loop treatment of intractable epilepsy is presented. Its triple-band radio with a 1m 230Mbps pulse-radio, a 2m 46Mbps pulse-radio 2, and a 10m 1.2Mbps FSK radio provides a versatile transcutaneous interface. The in-implant processor has constrained computational resources which results in a limited detection performance - seizure detection sensitivity of 87%. A higher-performance signal processing algorithm implemented on a stationary device within a loop enhances the seizure detection performance which was improved to a sensitivity of 98% with three times fewer false alarms. This comes at the cost of an increased wireless transmitter power budget, if communicated directly. These results illustrate a fundamental tradeoff between the communication and computation in closed-loop electronic therapies for neurological disorders.

A high slew-rate, two-stage, single-ended amplifier for optical imaging applications is reported. Two auxiliary circuits have been added to the core amplifier to boost the speed of the positive and negative slews. The amplifier is designed using parameters form IBM 0.13 μm technology. It achieves 41.2 dB DC gain, 723 MHz unity-gain bandwidth and 540 V/μs positive and 325 V/μs symmetric slew-rates for a load capacitance of 2 pF. A 357% symmetric improvement is achieved for slew rate while power is only increased by ∼3%. The core amplifier dissipates 98 μW from a 1.2 V supply.