Due to the convenience and electrostatic discharge (ESD)-free features, wireless power transfer (WPT) technology has become essential for mobile devices. Conventional WPT solutions use symmetrical inductive couplers with complex structures to enhance misalignment tolerance, while using a large transmitter (TX) coil with a small receiver (RX) coil can increase distance but results in lower power density. On the contrary, we employ in this paper small TX coil and large RX coil for a better tradeoff between power transfer efficiency (PTE), output power and robustness. With detailed analyses, we prove that the small TX large RX configuration outperforms the conventional large TX coil and small RX coil solution and derives the necessary conditions with design procedures for achieving optimal PTE and desired output power. An experimental setup is built to validate the analyses, revealing that the small TX large RX configuration achieves better PTE under the higher output power conditions. Specifically, the system with small TX large RX configuration attains a PTE of 98.7% at an output of 31.29W with an airgap of 10mm.

This paper proposes an inductor-first two-inductor two-flying-capacitor (2L2C) multi-path hybrid DC-DC Converter. The proposed converter operates with a switching frequency of 2MHz, an input voltage range of 3 V to 5 V, and an output range between 0.8 V and 1.2 V using only 2-V NMOS power transistors. This hybrid DC-DC topology enables continuous input current and thus alleviates electromagnetic interference (EMI) issues. The two inductors operate in an interleaved manner, reducing the output current ripple. The switched-capacitor network decreases the average inductor current. This work is simulated in a 180-nm BCD process. Both inductors are 470nH with 29-mΩ DCR, while both flying capacitors are 10μF with 10-mΩ ESR. We obtain a peak efficiency of 96.89% at 400 mA load for a 4V-to-1V conversion.

This paper presents a 12V-input 1.8V-0.8V-output multiple-output hybrid buck (MOHB) DC-DC converter with a shared flying-capacitor (CF0) and real-time CF0voltage calibration, while the main control loop uses a pulse-width modulation (PWM) control scheme. With the proposed time-interleaving operation scheme, the MOHB converter has no cross regulation during load transient. The real-time CF0voltage calibration ensures that the voltage across CF0 equals VIN/2. The MOHB converter is designed with four outputs and simulated in an 180nm BCD process. Each output employs a 1μH power inductor with 19mΩ DCR and one 4.7μF flying capacitor. With 12V input, one output equals to 1.8V and other outputs equal to 1V, the peak efficiency 95.2%.

This article presents a capacitorless linear low dropout regulator (LDO) with an N-type pass transistor that features high efficiency, fast transient and good power supply rejection (PSR) suitable for system-on-chip (SoC) integration. This LDO utilizes a pole-tracking compensation scheme and a transconductance-boosted (gm-boosted) folded-cascode EA to achieve high bandwidth. As a result, the LDO achieves a fast transient response and high PSR corner-frequency. Moreover, feedforward ripple cancellation (FFRC) is also incorporated to enhance the PSR performance further. The proposed LDO is fabricated in a 65nm CMOS process. It features PSR performance better than -65dB across the full load range at frequencies lower than 100kHz. And its undershoot and overshoot in response to a 1mA-to-100mA load transient with an edge time of 100ns are 83mV and 10mV, respectively.

Switched-capacitor-inductor dual-path hybrid DC-DC converter can achieve high power density and efficiency, with reduced inductor voltage and current stresses and thus reduced inductor conduction loss and volume. However, it suffers from a large output ripple due to the hard-charging of the switched-capacitor (SC). To take advantage of recent in-substrate or on-chip high-density capacitor technologies, this paper proposes a multiphase interleaving operation for the dual-path SC hybrid converter, increasing the equivalent switching frequency and reducing the amplitude of the current ripple. It achieves a significant output ripple reduction within negligible efficiency degradation. The analysis and simulation results prove that the proposed scheme is a better method for reducing output ripple than increasing operating frequency or reducing power transistor size in the hard-charging path.

This paper presents a scalable hybrid boost converter (SHBC) with adjusted number of stages (N) to acquire high conversion ratio (CR) and high power efficiency. Firstly, unlike most converters whereCRis related only to duty cycle (D), theCRof SHBC is related to bothDand N. This allows the converter to provide a highCRwhile keepingDat a reasonable value for easy loop control. Secondly, N flying capacitors in series with the inductor can divide output voltage ($V_{\mathrm {OUT}}$) to use low voltage devices with small figure of metric (FOM) for high power efficiency. Moreover, N flying capacitors in parallel with the inductor can shunt the inductor current to reduce the inductor DCR loss, which also helps improve power efficiency. Thirdly, when many N values meet the requirements of a specific application scenario, an optimal number of stages (NOPT) is proposed to minimize the total loss and optimize the power efficiency further. The prototype design of SHBC with$\mathrm{N}_{\mathrm {OPT}} =2$has been discussed and fabricated by$0.18~\mu $m BCD process. The measurement results demonstrate its operation is normal in theCRrange from 4 to 8. Besides, a 93.34% peak efficiency is also achieved with$I_{\mathrm {OUT}} =0.125$A andCR= 4.

This paper presents an enhanced three-level buck converter (E3LBC) with configurable power stage (CPS) and configurable control stage (CCS) for fast load transient response. Compared with the conventional 3LBC and existing solutions, the proposed CPS can raise the inductor current slope significantly by changing the switching node voltage to 3/2 times or -1/2 times the input voltage (VIN) during the load-increasing or load-decreasing transient, which will improve the load transient response. Moreover, the CPS can realize the series or parallel operations of flying capacitors (CF1,CF2) and make their voltages (VCF1,VCF2) eventually converge toVIN/2. On the other hand, the proposed CCS can eliminate the minimum off or on time by using hysteresis control and keep the inductor charging or discharging all the time during the load-increasing or load-decreasing transient for further improving load transient response. Besides, the CCS can provide an adaptive-on-time control in the steady state to acquire a pseudo-constant frequency for small output voltage ripple. The prototype design has been fabricated with the 0.18-μm CMOS process. According to the measurement results, the E3LBC exhibits undershoot/overshoot voltages and settling time of -19/+30 mV and 1.2/1.1 μs, when the load current is changed between 100 mA and 500 mA. The other measurements and comparisons also verify the effectiveness of CPS and CCS for the E3LBC.

When driving a GaN switch, the maximum transition speed of drain-source voltage (peak dv/dt) should meet specification. But reducing the peak dv/dt usually exacerbates V-I overlap loss. This work presents a GaN driver for buck converter featuring: 1) voltage-controlled peak dv/dt; 2) almost constant dv/dt during Miller Plateau (MP) for reducing V-I overlap loss. We analyze why a constant dv/dt minimizes V-I overlap loss under a peak dv/dt specification, how to maintain a constant dv/dt during the MP period, and propose an implementable solution. We use a sensing block to judge whether the peak dv/dt violates the specification, and an adaptive searching scheme to find out the key parameters for the targeted constant dv/dt. We designed the layout with a 180-nm SOI process, and simulation results show that the peak dv/dt is well under control. It saves up to 33.99% V-I overlap loss when compared with the conventional constant current driver scheme.

A Low-Dropout Regulator (LDO) with low quiescent current is proposed. The LDO uses a variable capacitance tracking zero compensation to enhance the stability within a wide load current range. Furthermore, it utilizes adaptive biasing current for a low quiescent current at the steady-state, while a transient enhancement circuit to improve transient response. Designed with a 65-nm CMOS process, the proposed LDO consumes a 5-nA quiescent current and supports a maximum 50-mA load current. The simulated output undershoot is 137 mV when the LDO has a load current step from 0 to 50 mA, with a 0.4-ns edge time.

This paper proposes a radio-frequency (RF) cross-connected (CC) rectifier with LC source degeneration (CCLC). The LC network resonates at twice of the working RF frequency, shaping the drain-source and gate-source voltages of the rectifying transistors of the CC rectifier. As a result, the proposed scheme reduces the transistors’ reverse current and the shoot-through current, and thus the root mean square current of the switches, improving the power conversion efficiency (PCE). Meanwhile, it has a better input impedance matching over a wide input power range from the voltage reshaping. Subsequently, we implement the CCLC topology in both one-stage and two-stage CC rectifiers. To reduce the silicon area, we design coupled inductors for the two LC networks of the two-stage CCLC rectifier. We fabricated the rectifiers using a 65-nm CMOS process. The measured PCE of the one-stage and two-stage rectifiers are 67.6% and 61.2%, respectively. The proposed scheme has a wider dynamic range than previous works.

This paper presents a single-inductor multiple-output (SIMO) DC-DC converter with fixed-frequency victim-last charge control. This scheme switches the load-transient channel (victim) to the last of the charging sequence, addressing the inherent cross-regulation issue in conventional charge control SIMO. We first analyze why the conventional fixed-frequency charge control has such an issue. Then, we present the working principle of the proposed scheme. After that, we propose a charge-error calibration technique that minimizes the side effects caused by victim-last control, ensuring a smooth order switching of the original last channel. We implemented and fabricated the proposed SIMO DC-DC converter in a 0.18-$\mu $m BCD process. Measurement results show that we are able to reduce the cross-regulation to 0.057mV/mA with a 225-mA load step under fixed switching frequency. The measured peak efficiency is 84.1%.

High-frequency buck converters need a fast transition of switching nodes (high dv/dt). Such high dv/dt, especially the positive one, can cause malfunction of a conventional pulse-triggered active-coupled (PTAC) level shifter that is used to control the high-side NMOS switch. In this work, we first discuss the dv/dt immunity of conventional PTAC level shifters. Subsequently, we propose a new scheme to block the noise current during the dv/dt sequence, allowing an almost full immunity to the positive dv/dt. With this scheme, the maximum dv/dt is determined by how well the circuitry is protected from the overvoltage during the dv/dt sequence. We design a 20-V buck converter with this level shifter, fabricated in 180-nm BCD process. Experimental results show it works correctly under a 67-V/ns dv/dt.

The series-capacitor boost converter (SCBC) requires a duty cycle ($D) \ge0.5$control, otherwise has issues of power switch overstress and inductor currents imbalance. Then, we cannot use the SCBC in wide conversion ratio (CR) applications that requireCR$D \ge0.5$control does not allow$D$to increase smoothly from 0 during start-up, causing severe inrush inductor currents. As a solution, we propose two control schemes on the capacitor-cross-connected (CCC) boost converter, which is the symmetric version of the SCBC. With the proposed hard-charging control, the CCC converter allows$D < 0.5$without overstress or imbalance issues, thus extending theCRrange and facilitating a soft start-up. In addition, we propose a soft-charging control that enhances the efficiency for 3CRCRexpressions under these two types of controls. Finally, we propose a compact centrosymmetric floorplan that reduces the switching nodes’ ringing, verifying the proposed schemes with a 2.8-to-8.4-V input / 24-V output prototype converter. It exhibits a soft start-up with the proposed control. Under an 8-V input voltage and 1.5-A output current, the peak efficiency of the proposed hard-charging and soft-charging control is 94.7% and 96.3%, respectively.

In this paper, we propose a scheme to design the reconfigurable filtering power divider with arbitrary operating channels based on external quality factor ($Q_{\mathbf {e}}$) control. By using an input feeding line,${n}$resonators, and$m$output feeding lines, the$n^{\mathbf {th}}$-order$m$-way filtering power divider topology can be obtained with a simple configuration. A coupled-line output feeding structure loading with multiple PIN diodes is proposed to adjust the output$Q_{\mathbf {e}}$values. Design theories for obtaining the desired$Q_{\mathbf {e}}$values are provided. Then, the filtering power divider can be fully reconfigured in the states with one to$m$operating channels. Good input matching can be achieved without using an additional reconfigurable impedance matching network in all these states, resulting in a size and loss reduction. For verification, a 2nd-order 4-way reconfigurable filtering power divider is designed, fabricated, and measured. As compared to the reported reconfigurable power dividers, the proposed design shows the merits of fully reconfigurable operating channels, favorable filtering responses, low insertion losses, high isolation, and a simple structure.

SUMMARY: We developed the MicrobiomeExplorer R package to facilitate the analysis and visualization of microbial communities. The MicrobiomeExplorer R package allows a user to perform typical microbiome analytic workflows and visualize their results, either through the command line or an interactive Shiny application included with the package. In addition to applying common analytical workflows, the application enables automated analysis report generation. AVAILABILITY AND IMPLEMENTATION: Available at https://github.com/zoecastillo/microbiomeExplorer. SUPPLEMENTARY INFORMATION: Supplementary data are available at Bioinformatics online.

In this paper, a sparse FIR filter design method based on cascaded compensation structure is proposed. The proposed method is a two-stage filter design approach with novel attenuation and transition controls of the subfllters. The model filter is elaborately designed with decreasing stopband attenuation to improve the sparsity of the filter. A compensating filter with careful transition band and stopband design is cascaded with the model filter to compensate the decreasing stopband attenuation of the model filter so as to synthesize the desired uniform attenuation. Simulation results show that the proposed cascaded compensation design of sparse FIR filters leads to a significant improvement of sparsity than the exiting conventional direct form or transposed direct form filter designs.

SUMMARY: BreakPoint Surveyor (BPS) is a computational pipeline for the discovery, characterization, and visualization of complex genomic rearrangements, such as viral genome integration, in paired-end sequence data. BPS facilitates interpretation of structural variants by merging structural variant breakpoint predictions, gene exon structure, read depth, and RNA-sequencing expression into a single comprehensive figure. AVAILABILITY AND IMPLEMENTATION: Source code and sample data freely available for download at https://github.com/ding-lab/BreakPointSurveyor, distributed under the GNU GPLv3 license, implemented in R, Python and BASH scripts, and supported on Unix/Linux/OS X operating systems. CONTACT: [email protected]. SUPPLEMENTARY INFORMATION: Supplementary data are available at Bioinformatics online.