Spiking Neural Networks (SNNs) offer a low-power alternative to conventional deep neural networks by leveraging their sparse, event-driven processing for both static and event-based data. While previous spiking autoencoders were energy-intensive and limited to static inputs, this work presents a novel spiking autoencoder capable of efficiently reconstructing both static and spatiotemporal data with high fidelity. To benchmark spatial pattern reconstruction, we evaluate performance on the MNIST and Fashion-MNIST datasets. Our autoencoder encodes each static input using just a single spike, reducing total energy consumption to an estimated 2.54 mJ across the entire training and testing phases. We also propose a novel decoder neuron model that enables fine-grained control over output spike timing, achieving over a 1000 × improvement in reconstruction quality compared to prior unsupervised Spike Timing Dependent Plasticity (STDP)-based methods. Additionally, we show that our model’s reconstruction performance is close to state-of-the-art autoencoders that rely on computationally intensive supervised, gradient-based convolutional networks. To validate performance on spatiotemporal data, we use the Spiking Heidelberg Digits (SHD) dataset and examine the trade-off between energy efficiency and reconstruction accuracy. Our results show that the reconstructions preserve most of the original information, while capping total energy use at 127 mJ for the full training and testing cycle. These findings lay a foundation for designing more efficient and scalable SNNs for real-world applications.

This paper presents an analysis of the application of an intentionally mismatched capacitive Digital-to-Analog Converter (CDAC) to improve the area efficiency and accuracy of successive-approximation register (SAR) analog-to-digital converters. The proposed SAR ADC architecture, the redundant capacitor-saver SAR ADC, utilizes 1-bit redundancy with intentional mismatch to estimate an additional resolution bit. This redundancy bit not only enhances noise tolerance but also achieves higher resolution through area- and energy-efficient computations, without requiring the addition of non-ideal, area-consuming, and energy-intensive capacitors to the CDAC block of the conventional SAR ADC. Simulations were conducted using Cadence TSMC 130nm CMOS technology and MATLAB software for conventional, redundant, and redundant capacitor-saver SAR ADCs, demonstrating 3 dB and 2 dB improvements in SNDR and SFDR, respectively, when using the capacitor-saver DAC architecture.

This paper proposes Matrix Sorting (MATSORT), a novel algorithm for compressing sparse matrices to enable efficient execution of sparse Multiply-Accumulate (MAC) operations in parallel computing architectures for Deep Neural Networks (DNNs). Pruning in DNNs often results in weight matrices with a large proportion of zero weights, leading to significant resource and time wastage when processed by parallel computing architecture. MATSORT outperforms state-of-the-art (SoTA) techniques in both compression speed and compression rate—two key factors for efficient sparse MAC operations. The algorithm employs an approximate sorting method and a novel merging strategy, reducing the sorting time complexity while resolving long-standing element conflict issues. These optimizations achieve nearly 100% compression rates across all tested matrices, substantially enhancing power and resource efficiency. Evaluation results show that MATSORT delivers a maximum speedup of 441× for a 1280 × 1280 matrix and a minimum speedup of 1.63× for a 110 × 128 matrix, outperforming existing methods.

Spiking Auto-Encoders (SAEs) have the potential to greatly outperform deep learning auto-encoders in power efficiency, yet their performance remains a challenge. This work enhances both power efficiency and accuracy by reducing spike counts and introducing key innovations. We propose a novel decoder neuron model that enables precise spike timing and implement a weight-dependent Spike-Timing-Dependent Plasticity (STDP) mechanism in the encoder for better feature learning. Our architecture encodes static MNIST images using only a single spike and reconstructs spatio-temporal data from the Spiking Heidelberg Digits (SHD) dataset, optimizing the spike count for reconstruction. This substantial reduction in spike usage translates to a marked improvement in power efficiency. In addition, the average Mean Square Error (MSE) for the MNIST images was found to be 0.039, representing a 99.93% reduction from previous results. These improvements advance neuromorphic systems toward more practical, efficient applications.

This paper conducts a detailed analysis of the impact of channel charge injection on the capacitive digital-to-analog (DAC) block in successive-approximation register (SAR) analog-to-digital converters (ADCs). It introduces a CAD tool for distinguishing various non-idealities, quantifying channel charge injection across all possible binary output codes. It enables the implementation of more effective compensation methods rather than relying on simple dummy switches by detecting most effective switches. All simulations are conducted using Cadence TSMC 130nm CMOS technology and MATLAB software, implying on 5 to 7 dB degradation in SNDR when considering the effect of channel charge injection in 6, 9, and 12-bit typical SAR ADCs.

Transformers have emerged as the state-of-the-art architecture for natural language processing (NLP) and computer vision. However, they are inefficient in both conventional and in-memory computing architectures as doubling their sequence length quadruples their time and memory complexity due to their self-attention mechanism. Traditional methods optimize self-attention using memory-efficient algorithms or approximate methods, such as locality-sensitive hashing (LSH) attention that reduces time and memory complexity from O(L2) to O(L log L). In this work, we propose a hardware-level solution that further improves the computational efficiency of LSH attention by utilizing in-memory computing with semi-passive memristor arrays. We demonstrate that LSH can be performed with low-resolution, energy-efficient 0T1R arrays performing stochastic memristive vector-matrix multiplication (VMM). Using circuit-level simulation, we show our proposed method is feasible as a drop-in approximation in Large Language Models (LLMs) with no degradation in evaluation metrics. Our results set the foundation for future works on computing the entire transformer architecture in-memory.

Conventional surrogate Back-Propagation-Through-Time learning in Spiking Neural Networks (SNN) demands excessive energy consumption when simulating over extended time intervals. Moreover, the spike encoding process necessitates intricate hardware support, thus undermining overall efficiency. Additionally, their classification accuracies fall short in comparison to artificial neural networks due to the inherent information loss in spike translation. Therefore, there is a critical need for efficient techniques that can enhance performance without compromising accuracy. In this study, we introduce a novel learning scheme that harnesses lossless phase coding. This approach allows us to achieve minimal inference latency, requiring a maximum of at most 8 simulation steps. Furthermore, our training times exhibit significant reductions when compared to previous single-spike networks. Our experimental results demonstrate that Phase-SNN attains state-of-the-art accuracy levels, achieving 98.6% and 89.6% accuracies on the MNIST and Fashion-MNIST datasets, respectively.

In this work, we present a memristor crossbar array-based hardware architecture designed to solve a system of differential equations for the Hodgkin-Huxley neuron model. The system extends from previous works to perform more computations in-memory, reducing the load of software processing and distributing them onto memristive hardware along with cheap shift-and-add operations. We demonstrate the properties of the solutions produced by the system follow the expected behaviours of the Hodgkin-Huxley model under various external currents.

As machine learning (ML) algorithms, particularly neural networks (NN), expand in popularity and capacity, the quest for more efficient computation methods gains momentum. Memristor crossbar technology emerges as a promising alternative to traditional computing units, aiming to address traditional computing challenges. However, conventional matrix-vector multiplication (MVM) methods on these platforms are often plagued by device imperfections and drift. In this work, we introduce an innovative lightweight calculation approach leveraging bit-transformation for MVM, significantly enhancing operation precision and, consequently, the performance of ML algorithms on memristor crossbar platforms. We provide details of the core algorithm and its extensions, furnish digital validation, and simulate its efficacy using an autoencoder (AE) neural network with an extended VTEAM model. Our tests demonstrate an average reconstruction precision improvement of approximately 53.5%. This work’s applicability extends beyond NNs, offering a foundational method for conducting more precise analog MVM operations.

Auto-encoders are capable of performing input re-construction through an encoder-decoder structure. These net-works can serve many purposes such as noise removal and anomaly detection, whilst being trained without the need for labelled data. Spiking auto-encoders can utilise asynchronous spikes to potentially improve power and simplify the required hardware. In this work, we propose an efficient spiking auto-encoder with novel error-modulated STDP learning. Our auto-encoder uses the Time To First Spike (TTFS) encoding scheme and needs to update all synaptic weights only once per input. Also, it needs only an average of 8 spikes in its hidden layer for reconstruction, leading to a very sparse and hence potentially power-efficient implementation. We demonstrate decent reconstruction ability for MNIST and the challenging Caltech Face/Motorbike datasets and achieve excellent noise removal from MNIST images.

This paper presents a hybrid pipeline SAR ADC with a loop-unrolled structure to reduce the crossbar’s ADC power while maintaining high speed. The 1ststage memristive SAR ADC can fully utilize the TIA originally in the crossbar and avoid the extra MDAC in pipeline ADC. Further, memristive weight calibration and a new resistive alternated binary search are implemented on the 1ststage to maintain the TIA gain and ADC’s accuracy. Both stage’s ADC are loop-unroll to eliminate the delay brought by SAR logic for high speed. Through multiple simulations, the design is demonstrated to be robust to the frequency and mismatch variations with the highest sampling frequency reaching 300MHz and SNDR up to 65.1dB in 9MHz input. The power consumption is designed to be as low as 6.7mW, which helps the ADC to achieve a 15.2fJ/conv FoM. Not limited to the crossbar, the presented ADC also shows promising potential for applications in various fields (biomedical, IoT etc.) for general purposes.

Von Neumann architecture-based deep neural network architectures are fundamentally bottlenecked by the need to transfer data from memory to compute units. Memristor crossbar-based accelerators overcome this by leveraging Kirchoff's law to perform matrix-vector multiplication (MVM) in-memory. They still, however, are relatively inefficient in their device programming schemes, requiring individual devices to be written sequentially or row-by-row. Parallel writing schemes have recently emerged, which program entire crossbars simultaneously through the outer product of bit-line and word-line voltages and pulse widths respectively. We propose a scheme that leverages singular value decomposition and low-rank approximation to generate all word-line and bit-line vectors needed to program a convolutional neural network (CNN) onto a memristive crossbar-based accelerator. Our scheme reduces programming latency by 90% from row-by-row programming schemes, while maintaining high test accuracy on state of the art image classification models.

A universal objective function to minimize mem-ristive crossbar deep neural network weight mapping errors through Hessian backpropagation (HessProp) is presented. Hes-sProp minimizes the$L_{2}$norm of the neural network gradient to achieve a flat minima in a neural network's weight space. We hypothesize that this leads to robustness against small perturbations of weights. The stochastic weight mapping phe-nomenon on memristor crossbars is simulated, and the proposed method was evaluated on image classification tasks using the MNIST dataset. The result demonstrates on average 40.81% and 41.45% groundbreaking accuracy increase for distilled and large memristive convolutional neural networks in worst-case scenarios.

In this work, ensemble methods are presented and tested as universal ways to improve the performance of Memristive Deep Neural Networks (MDNNs) with non-idealities. The Generalized Ensemble Method and Weighted Voting ensemble methods improve the accuracy of classification on the MNIST dataset by 6.5% and 6.6% respectively, thus showing that they are more effective than basic Ensemble Averaging which has been investigated before, as well as other methods such as Voting. Different weighting schemes for Weighted Voting were tested, and we present Algorithm 1 and 2, which are the theoretically and experimentally optimal weighting schemes respectively. Our work serves as a guideline for choosing ensemble methods for MDNNs.

In this work, we solve nonlinear systems of ordinary differential equations coupled to noisy forcing, commonly used for models of neurons such as the Hodgkin-Huxley equation, over a memristor crossbar based computing system. We demonstrate stability and faithfulness of the distributions even under the effects of nonidealities of the memristors and the system itself. We investigate the properties of the dynamical systems under quantization faithfulness, varying the level of precision of the fixed point integer representation and concluding that 24 bits is enough for solution of the Hodgkin-Huxley equations, demonstrating that our solver can operate with both high precision and achieve speedups with low precision approximate computation.

Single-cell RNA sequencing is an emerging technique in the field of biology that departs radically from the previous assumption of gene-expression homogeneity within a tissue. The large quantity of data generated by this technology enables discoveries of cellular biology and disease mechanics that were previously not possible, and calls for accurate, scalable, and efficient processing pipelines. In this work, we propose SSCAE (spiking single-cell autoencoder), a novel SNN-based autoencoder for sc-RNA-seq dimensionality reduction. We apply this architecture to a variety of datasets, and the results show that it can match and surpass the performance of current state-of-the-art techniques. Moreover, the potential of this technique lies in its ability to be scaled up and to take advantage of neuromorphic hardware, circumventing the memory bottleneck that currently limits the size of sequencing datasets that can be processed.

In this work, PRUNIX, a framework for training and pruning convolutional neural networks is proposed for deployment on memristor crossbar based accelerators. PRUNIX takes into account the numerous non-ideal effects of memristor crossbars including weight quantization, state-drift, aging and stuck-at-faults. PRUNIX utilises a novel Group Sawtooth Regularization intended to improve non-ideality tolerance as well as sparsity, and a novel Adaptive Pruning Algorithm (APA) intended to minimise accuracy loss by considering the sensitivity of different layers of a CNN to pruning. We compare our regularization and pruning methods with other standards on multiple CNN architectures, and observe an improvement of 13% test accuracy when quantization and other non-ideal effects are accounted for with an overall sparsity of 85%, which is similar to other methods.

We present a novel cryptography architecture based on memristor crossbar array, binary hypervectors, and neural network. Utilizing the stochastic and unclonable nature of memristor crossbar and error tolerance of binary hypervectors and neural network, implementation of the algorithm on memristor crossbar simulation is made possible. We demonstrate that with an increasing dimension of the binary hypervectors, the nonidealities in the memristor circuit can be effectively controlled. At the fine level of controlled crossbar non-ideality, noise from memristor circuit can be used to encrypt data while being sufficiently interpretable by neural network for decryption. We applied our algorithm on image cryptography for proof of concept, and to text en/decryption with 100% decryption accuracy despite crossbar noises. Our work shows the potential and feasibility of using memristor crossbars as an unclonable stochastic encoder unit of cryptography on top of their existing functionality as a vectormatrix multiplication acceleration device.

The impact of device and circuit-level effects in mixed-signal Resistive Random Access Memory (RRAM) accelerators typically manifest as performance degradation of Deep Learning (DL) algorithms, but the degree of impact varies based on algorithmic features. These include network architecture, capacity, weight distribution, and the type of inter-layer connections. Techniques are continuously emerging to efficiently train sparse neural networks, which may have activation sparsity, quantization, and memristive noise. In this paper, we present an extended Design Space Exploration (DSE) methodology to quantify the benefits and limitations of dense and sparse mapping schemes for a variety of network architectures. While sparsity of connectivity promotes less power consumption and is often optimized for extracting localized features, its performance on tiled RRAM arrays may be more susceptible to noise due to under-parameterization, when compared to dense mapping schemes. Moreover, we present a case study quantifying and formalizing the trade-offs of typical non-idealities introduced into l-Transistor-l-Resistor (ITIR) tiled memristive architectures and the size of modular crossbar tiles using the CIFAR-10 dataset.

Here we present stochastic differential equations (SDEs) on a memristor crossbar, where the source of gaussian noise is derived from the random conductance due to ion drift in the devices during programming. We examine the effects of line resistance on the generation of normal random vectors, showing the skew and kurtosis are within acceptable bounds. We then show the implementation of a stochastic differential equation solver for the Black-Scholes SDE, and compare the distribution with the analytic solution. We determine that the random number generation works as intended, and calculate the energy cost of the simulation.

Memristor crossbar architectures are considered as one of the most promising platforms for future memory, logic, and in-memory computing applications. This paper presents a 2M1M crossbar architecture, capable of memory and logic applications, based on a transistor-less memory cell, which behaves as a switching circuit. The proposed memory cell consists of two access and one target memristors that utilize a gating structure by access devices to reduce sneak path effect. This paper has considerably lower wiring density and lower number of memristors per bit compared with its peers. Therefore, it can be a suitable structure for high-density memory and logic applications. In addition to its in-memory computing capabilities, 2M1M structure as a memory offers higher density and less energy consumption in comparison with conventional CMOS-based static random access memory. In comparison with previous works, simulation results show significant improvements in basic implementation costs of the memory cell in terms of write time (1.11 ns), read time (200 ps), density (80 Gb/cm2), energy consumption (23.2 × 10-3fJ/bit), and wiring complexity. Also, it has a sneak path current of 90-nA per memory cell operation which is considerably lower compared with its peers.

These days, there is an increasing interest in implementation of spiking neural systems that can be used to perform complex computations or solve pattern recognition tasks like mammalian neocortex. In this paper, Morris-Lecar neuron neuron is utilized to implement bio-inspired memristive spiking neural network for unsupervised learning applications. The spike timing dependent plasticity learning mechanism has been applied as the learning scheme in the system. The memristive implementation of the Morris-Lecar neuron has been analyzed. Also the memristors are utilized as the synapses for the proposed system to reproduce long term potentiation and long term depression. The proposed platform is tested for pattern classification applications and the results are successfully confirmed its functionality.

Memristor-based arithmetic circuits promise new alternatives for their conventional CMOS-based peers due to memristor' s scalability and non-volatility features. In-memory memristor-based calculations become extensively attractive as it can be a solution to tackle memory bottleneck problems and also an ingredient for future beyond Von-Neumann computer architectures. In this paper material implication-based designs for 4:2 compressor cells using memristor devices are presented. A physical model is applied to determine real switching speed of memristive device. The proposed parallel design promises good speed performance with considerably less area than conventional CMOS designs. Finally a comparison has been made between the proposed memristor-based and CMOS-based designs in terms of number of applied devices per cell and delay.

In this paper, design of a passive resistive-type neuron is proposed to generate the hyperbolic tangent function as the activation function. The proposed resistive-type neuron has the advantage of not needing any biasing voltage and therefore its power consumption is low. The neuron circuit is designed and simulated in 180 nm CMOS technology. The proposed neuron shows a good approximation with maximum error and average error from the ideal hyperbolic tangent function by 19.7% and 6.88% respectively. The power consumption of the proposed neuron is 62.5 μW while the standby power is zero. Also the proposed neuron is applied in a large neural network and the results shows good functionality. The pattern recognition neural network implemented using the proposed neuron is consumed 295 μW power that is approximately 59.86% less than the same network proposed with the previous analog hyperbolic tangent designed neuron.