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Alessandro Sansonetti

dblp:157/9085 · DBLP profile ↗
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5ranked-venue papers
0as first author
0since 2021 · last 2019
—ORCID · none

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 5Software engineering, systems software and programming languages · 2

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
1 paper
Electronic design automation · 67% Embedded and real-time systems · 33%

Topics — the 3 heaviest of 3, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Embedded and real-time systems › automotive embedded systems
automotive microcontroller
0.212016
Development Flow for On-Line Core Self-Test of Automotive Microcontrollers · IEEE Trans. Computers 2016
Electronic design automation
hardware verification and test
0.212016
Development Flow for On-Line Core Self-Test of Automotive Microcontrollers · IEEE Trans. Computers 2016
Electronic design automation › hardware verification and test › design for testability › built-in self-test
software-based self-test
0.212016
Development Flow for On-Line Core Self-Test of Automotive Microcontrollers · IEEE Trans. Computers 2016

Methods — techniques the papers use, named apart from their topics

test program generation · 0.2stuck-at fault coverage · 0.2
YearPublicationVenuePosition
2019 Non-Intrusive Self-Test Library for Automotive Critical Applications: Constraints and Solutions
abstract
Today, safety-critical applications require self-tests and self-diagnosis approaches to be applied during the lifetime of the device. In general, the fault coverage values required by the standards (like ISO 26262) in the whole System-on-Chip (SoC) are very high. Therefore, different strategies are adopted. In the case of the processor core, the required fault coverage can be achieved by scheduling the periodical execution of a set of test programs or Software-Test Library (STL). However, the STL for infield testing should be able to comply with the operating system specifications without affecting the mission operation of the device application. In this paper, the most relevant problems for the development of the STL are first discussed. Then, it presents a set of strategies and solutions oriented to produce an efficient and non-intrusive STL to be used exclusively during the in-field testing of automotive processor cores. The proposed approach was experimented on an automotive SoC developed by STMicroelectronics.
Paolo Bernardi 0002, Riccardo Cantoro, Andrea Floridia, Davide Piumatti, C. Pogonea, Annachiara Ruospo, Ernesto Sánchez 0001, Sergio de Luca, Alessandro Sansonetti
DATE9
2017 Robustness in automotive electronics: An industrial overview of major concerns
abstract
Different perspectives about the concept of Robustness in Automotive Electronic are provides by leading edge semiconductor manufacturer. Xilinx contribution is related to the development and evaluation of Software Test Libraries suitable for in-field testing of the interconnect blocks in large SoCs. Infineon (IFX) section is discussing safety and security concerns of On-Line FLASH Memory Repair. STMicroelectronics is providing guidelines for the development and integration of Core Self-Test libraries.
Ulrich Backhausen, Oscar Ballan, Paolo Bernardi 0002, Sergio de Luca, Julie Henzler, Thomas Kern, Davide Piumatti, Thomas Rabenalt, Krishnapriya Chakiat Ramamoorthy, Ernesto Sánchez 0001, Alessandro Sansonetti, Rudolf Ullmann, Federico Venini, Robert Wiesner
IOLTS11
2017 On the in-field testing of spare modules in automotive microprocessors
abstract
Currently, the most of the available strategies devised for in-field testing of microprocessor cores in the automotive market, are mainly oriented to test the more representative functional modules. However, most of the modern architectures also include a series of spare computational components that perform very specific functionalities. For example, merging modules, masked and reverse operation modules, circular buffers, and special counters able to speed up the final application. In this paper, we provide a set of guidelines for the generation of Software-Based Self-Test programs that can be used to functionally test these modules during the in-field operation of the processor core. For every one of these modules, ad-hoc techniques are illustrated. The experimental results were gathered on two different multi-core designs manufactured by STMicroelectronics.
Paolo Bernardi 0002, Sergio de Luca, Davide Piumatti, S. Regis, Ernesto Sánchez 0001, Alessandro Sansonetti
VLSI-SoC6
2016 Development Flow for On-Line Core Self-Test of Automotive Microcontrollers
abstract
Software-Based Self-Test is an effective methodology for devising the online testing of Systems-on-Chip. In the automotive field, a set of test programs to be run during mission mode is also called Core Self-Test library. This paper introduces many new contributions: (1) it illustrates the several issues that need to be taken into account when generating test programs for on-line execution; (2) it proposed an overall development flow based on ordered generation of test programs that is minimizing the computational efforts; (3) it is providing guidelines for allowing the coexistence of the Core Self-Test library with the mission application while guaranteeing execution robustness. The proposed methodology has been experimented on a large industrial case study. The coverage level reached after one year of team work is over 87 percent of stuck-at fault coverage, and execution time is compliant with the ISO26262 specification. Experimental results suggest that alternative approaches may request excessive evaluation time thus making the generation flow unfeasible for large designs.
Paolo Bernardi 0002, Riccardo Cantoro, Sergio de Luca, Ernesto Sánchez 0001, Alessandro Sansonetti
IEEE Trans. Computers5
2015 Software-based self-test techniques of computational modules in dual issue embedded processors
abstract
Self-Test strategies for testing embedded processors are increasingly diffused. In this paper, we describe a set of self-test techniques tackling dual issue embedded processors. The paper details how to produce test programs suitable to detect stuck-at faults in computational modules belonging to dual issue processors. The proposed technique is aimed at extending single issue test programs; results are illustrated for a 32-bit processor included in an automotive System-on-Chip manufactured by STMicroelectronics and implementing a dual issue strategy with static dispatch of instructions.
Paolo Bernardi 0002, C. Bovi, Riccardo Cantoro, Sergio de Luca, Renato Meregalli, Davide Piumatti, Ernesto Sánchez 0001, Alessandro Sansonetti
ETS8