CASTLE is a Compression-based main memory Architecture realizing a read-decrypt-free (i.e., write-only) Secure solution for low laTency, Low Energy, high endurance non-volatile memories (NVMs). CASTLE integrates pattern-based data compression and incomplete data mapping (i.e., expansion coding) to improve NVM energy, latency, and lifetime without impacting the security guarantees of the underlying security architecture. System-level simulations of a TLC RRAM architecture show that CASTLE reduces memory energy by 19% and write latency by 38.7%, and improves lifetime by 1.8× over state-of-the-art solutions for NVM security.

RAPID is a low-overhead critical-word-first read acceleration architecture for improved performance and endurance in MLC/TLC non-volatile memories (NVMs). RAPID encodes the critical words in a cache line using only the most significant bits (MSbs) of the MLC/TLC NVM cells. Since the MSbs of an NVM cell can be decoded using a single read strobe, the data (i.e., critical words) encoded using the MSbs can be decoded with low latency. System-level SPEC CPU2006 workload evaluations of a TLC RRAM architecture show that RAPID improves read latency by 21%, energy by 24%, and endurance by 2-4× over state-of-the-art striped NVM.

Multilevel/triple-level cell nonvolatile memories (MLC/TLC NVMs) such as phase-change memory (PCM) and resistive RAM (RRAM) are the subject of active research and development as replacement candidates for DRAM, which is limited by its high refresh power and poor scaling potential. In addition to the benefits of nonvolatility (low refresh power) and improved scalability, MLC/TLC NVMs offer high data density and memory capacity over DRAM. However, the viability of MLC/TLC NVMs is limited primarily due to the high programming energy and latency as well as the low endurance of NVM cells; these are primarily attributed to the iterative program-and-verify procedure necessary for programming the NVM cells. This article proposes compression-expansion (CompEx) coding, a low overhead scheme that synergistically integrates pattern-based compression with expansion coding to realize simultaneous energy, latency, and lifetime improvements in MLC/TLC NVMs. CompEx coding is agnostic to the choice of compression technique; in this work, we evaluate CompEx coding using both frequent pattern compression (FPC) and base-delta-immediate (BΔI) compression. CompEx coding integrates FPC/BΔI with ( k , m ) q “expansion” coding; expansion codes are a class of q -ary linear block codes that encode data using only the low energy states of a q -ary NVM cell. CompEx coding simultaneously reduces energy and latency and improves lifetime for negligible-to-no memory overhead and negligible logic overhead (≈ 10k gates, which is <0.1% per NVM module). Furthermore, we also propose CompEx++ coding, which extends CompEx coding by leveraging the variable compressibility of pattern-based compression techniques. CompEx++ coding integrates custom expansion codes to each of the compression patterns to exploit maximum energy/latency benefits of CompEx coding. Our full-system simulations using TLC RRAM show that CompEx/CompEx++ coding reduces total memory energy by 57%/61% and write latency by 23.5%/26%; these improvements translate to a 5.7%/10.6% improvement in IPC, a 11.8%/19.9% improvement in main memory bandwidth, and 1.8 × improvement in lifetime over classical binary coding using data-comparison write. CompEx/CompEx++ coding thus addresses the programming energy/latency and lifetime challenges of MLC/TLC NVMs that pose a serious technological roadblock to their adoption in high-performance computing systems.

Emerging nonvolatile memories (NVMs) suffer from low write endurance, resulting in early cell failures (hard errors), which reduce memory lifetime. It was recognized early on that conventional error-correcting codes (ECCs), which are designed for soft errors, are a poor choice for addressing hard errors in NVMs. This led to the evolution of hard error correction schemes like dynamically replicated memory (DRM), error-correcting pointers (ECPs), SAFER, FREE-p, PAYG, and Zombie memory to improve NVM lifetime. Whereas these approaches made significant inroads in addressing hard errors and low memory lifetime in NVMs, overcoming the challenges of underutilization of error-correcting resources and/or implementation overhead (e.g., codec latency, hardware support) remain areas of active research and development. This article proposes error-correcting strings (ECSs) as a high-utilization, low-latency solution for hard error correction in single-/multi-/triple-level cell (SLC/MLC/TLC) NVMs. At its core, ECS adopts a base-offset approach to store pointers to the failed memory cells; in this work, base is the address of the first failed cell in a memory block and offsets are the distances between successive failed cells in that memory block. Unlike ECP, which uses fixed-length pointers, ECS uses variable-length offsets to point to the failed cells, thereby realizing more pointers to tolerate more hard errors per memory block. Further, this article proposes eXtended-ECS (XECS), a page-level error correction architecture, which employs dynamic on-demand ECS allocation and opportunistic pattern-based data compression to improve NVM lifetime by 2× over ECP-6 for comparable overhead and negligible impact to system performance. Finally, this article demonstrates that ECS is a drop-in replacement for ECP to extend the lifetime of state-of-the-art ECP-based techniques like PAYG and Zombie memory; ECS is also compatible with MLC/TLC NVMs, where it complements drift-induced soft error reduction techniques like ECC and incomplete data mapping to simultaneously extend NVM lifetime.

Multi-level/triple-level cell non-volatile memories (MLC/TLC NVMs) such as PCM and RRAM are the subject of active research and development as replacement candidates for DRAM, which is limited by its high refresh power and poor scaling potential. Besides the benefits of non-volatility (low refresh power) and improved scalability, MLC/TLC NVMs offer high data density and memory capacity over DRAM. However, the viability of MLC/TLC NVMs is limited primarily due to the high programming energy and latency as well as the low endurance of NVM cells; these are primarily attributable to the iterative program-and-verify procedure necessary for programming the NVM cells. In this paper, we propose compression-expansion (CompEx) coding, a low overhead scheme that synergistically integrates statistical compression with expansion coding to realize simultaneous energy, latency, and lifetime improvements in MLC/TLC NVMs. CompEx coding is agnostic to the choice of compression technique; in this paper, we evaluate CompEx coding using both frequent pattern compression (FPC) and base-delta-immediate (BΔI) compression. CompEx coding integrates FPC/BΔI with (k, m)q `expansion' coding; expansion codes are a class of q-ary linear block codes that encode data using only the low energy states of a q-ary NVM cell. CompEx coding simultaneously reduces energy and latency and improves lifetime for no memory overhead and negligible logic overhead (≈ 10k gates, which is <; 0.1% per NVM module). Our full-system simulations of a system that integrates TLC RRAM show that CompEx coding reduces total memory energy by 53% and write latency by 24%; these improvements translate to a 5.7% improvement in IPC, a 11.8% improvement in main memory bandwidth, and 1.8× improvement in lifetime over classical binary coding using data-comparison write. CompEx coding thus addresses the programming energy/latency and lifetime challenges of MLC/-TLC NVMs that pose a serious technological roadblock to their adoption in high performance computing systems.

This paper describes a write-once-memory-code phase change memory (WOM-code PCM) architecture for next-generation non-volatile memory applications. Specifically, we address the long latency of the write operation in PCM-attributed to PCM SET-by proposing a novel PCM memory architecture that integrates the 〈22}2/3 WOM-code at the memory organization and memory controller levels. To further improve the write latency of WOM-code PCM, we propose a PCM-refresh approach that uses idle cycles to preemptively set PCM rows to the initial WOM-code state. Finally, to balance write latency improvements against WOM-code PCM overhead, we propose a WOM-code cached PCM (WCPCM) architecture that uses WOM-code PCM as the cache alongside conventional PCM main memory. Since WOM-code techniques inherently impact PCM endurance by increasing the number of bitwrites in comparison to unencoded PCM, we incorporate additional transitions from the 〈22}2/3 WOM-code transition graph to realize endurance-WOM-code (e-WOM-code) architectures. Transitions between the e-WOM-code states on writes to memory are integrated into an incremental coding for endurance (ICE) approach that exploits redundancies in the conventional WOM-code to reduce the number of bit-writes over unencoded PCM. Simulation results show that the proposed e-WOM-code PCM architecture is able to reduce memory write (read) latency by 19.8 percent (14.7 percent) and the number of bit-writes over unencoded PCM without (with) datacomparison write (DCW), a read-modify-write process that only updates changed cells, by 83.0 percent (22.1 percent) on average across general-purpose (SPEC CPU2006), embedded (MiBench), and high-performance (SPLASH-2) benchmarks. Further, e-WOMcode PCM with PCM-refresh can reduce memory write (read) latency by 51.5 percent (44.1 percent) and the number of bit-writes over unencoded PCM without DCW by 76.5 percent on average across the benchmarks; there is, however, an increase of 19 percent in the number of bit-writes over unencoded PCM with DCW. Finally, for just 4.7 percent memory overhead, the e-WOM-code cached PCM (e-WCPCM) architecture reduces memory write (read) latency by 47.5 percent (41.6 percent) and the number of bit-writes over unencoded PCM without DCW by 68.1 percent on average across the benchmarks; again, there is a 49 percent increase in the number of bit-writes over unencoded PCM with DCW.

This paper proposes Flip-Mirror-Rotate (FMR), an architecture for bit-write reduction and endurance enhancement in emerging non-volatile memories (NVMs). FMR comprises three components: adaptive Flip-N-Write (aFNW), Mirror-N-Write (MNW), and Rotate-N-Write (RNW). aFNW and MNW focus on word-level bit-write reduction, which reduces NVM dynamic energy while also improving endurance. RNW is an intra-word wear leveling scheme that operates at cache line granularity. The proposed FMR architecture is integrated with frequent pattern compression (FPC) to simultaneously reduce bit-writes and wear in NVMs. Trace-based simulations of the SPEC CPU2006 benchmarks show that for the same memory overhead and < 1% loss in memory bandwidth, FMR reduces bit-writes (dynamic energy) by 48% (29%) in comparison to classical read-modify-write (DCW), 39% (13%) in comparison to Flip-N-Write (FNW), and 21% (14%) in comparison to FPC. Simultaneously, FMR also reduces the peak bit-writes per cell by 47% in comparison to DCW, 34% in comparison to FNW, and 47% in comparison to FPC, improving NVM endurance.