This paper presents novel access patterns for P-parallel N-point radix-2 memory-based fast Fourier transform (FFT) architectures. This work aims to reduce the latency and increase the throughput by changing the data order and/or choosing different places of the architectures to input/output data. In this way, we can eliminate the loading time and/or the time to collect the output data. This results in a reduction in latency and an increase in throughput. Likewise, the architectures use the same permutation circuits for each iteration, which simplifies the circuit. In addition to improvements in latency and throughput with different access patterns for memory-based FFTs, this work also offers bit-reversed or natural input/output alternatives.

When the COVID-19 pandemic broke out in the beginning of 2020, it became crucial to enhance early diagnosis with efficient means to reduce dangers and future spread of the viruses as soon as possible. Finding effective treatments and lowering mortality rates is now more important than ever. Scanning with a computer tomography (CT) scanner is a helpful method for detecting COVID-19 in this regard. The present paper, as such, is an attempt to contribute to this process by generating an open-source, CT-based image dataset. This dataset contains the CT scans of lung parenchyma regions of 180 COVID-19-positive and 86 COVID-19-negative patients taken at the Bursa Yuksek Ihtisas Training and Research Hospital. The experimental studies show that the modified EfficientNet-ap-nish method uses this dataset effectively for diagnostic purposes. Firstly, a smart segmentation mechanism based on the k -means algorithm is applied to this dataset as a preprocessing stage. Then, performance pretrained models are analyzed using different CNN architectures and with our Nish activation function. The statistical rates are obtained by the various EfficientNet models and the highest detection score is obtained with the EfficientNet-B4-ap-nish version, which provides a 97.93% accuracy rate and a 97.33% F 1-score. The implications of the proposed method are immense both for present-day applications and future developments.

This paper presents a novel 64-parallel 4096-point radix-2 memory-based fast Fourier transform (FFT) architecture for 6G. This approach is the first one to use 64 parallel branches in memory-based architectures. The challenge of designing a memory-based FFT with such a high parallelization has been accomplished by paying special attention to the large number of memories in parallel. Their control has been simplified by using the same read and write address for all of them thanks to the perfect shuffle permutation, and they are organized in groups to eliminate unnecessary registers. Likewise, a novel design for the rotation memories allows for reusing rotation coefficients among parallel rotators, and a new design for the circular counter that controls the architecture is presented. The proposed FFT architecture has been implemented on a Virtex 7 field-programmable gate array (FPGA). Experimental results reveal that the proposed architecture achieves the lowest latency in clock cycles and the highest throughput in samples per clock cycle among memory-based FFT architectures so far.