Elliptic Curve Cryptography and PKI have supported secure V2X communication for many years. With the expected impact of quantum computing on classical signatures, several studies have examined post-quantum alternatives. Early work, however, showed that replacing ECDSA with lattice-based schemes introduces practical difficulties: Dilithium signatures and certificates add more than 7 kB of extra data, cause fragmentation on the wireless channel, and increase delay to levels that are hard to use in time-critical V2X links. This paper presents Q-Auth5G, an integrated post-quantum authentication method designed for 5G-V2X. The protocol derives Dilithium3 and Kyber768 credentials directly from the 5G-AKA key chain, removing the need for repeated certificate transmission. A dual-beacon structure is adopted: the larger FULL beacon is used only when necessary, while the lighter REF beacon and the periodic BSM carry most traffic under a symmetric session key. The system was evaluated in urban, highway, rural, and dense city-centre settings. The V2I bootstrap completes in 2.28 ms, and V2V establishment requires 0.41 ms. Regular BSM cryptographic processing averages 0.049 ms. These results show a substantial gain over earlier PQ-V2X studies, where authentication times ranged from 1.3 ms to more than 300 ms. The conditional beaconing method reduces the average beacon size to 140–262 bytes (scenario-dependent), a reduction of over 97% compared with full certificate transmission. Delivery ratios stayed high, with 95.7–98.5% for beacons and 96.4–99.1% for BSMs. Security testing reported prevention rates of 100% for impersonation and Sybil attacks, 91–100% for replay, and 97–100% for man-in-the-middle attempts. The results indicate that Q-Auth5G offers a practical, backward-compatible, and quantum-resistant authentication layer suitable for future intelligent transportation systems.

Quantum computing threatens the cryptographic foundations of Vehicle-to-Everything (V2X) security. We present PQ-V2X, a large-scale dataset and benchmarking suite for post-quantum intrusion detection that integrates cryptographic artifacts, vehicular mobility, and zone-aware channel conditions. The dataset comprises five million labeled records spanning 23 attack types across post-quantum, hybrid, and classical families, including 10.05% real traces generated from Kyber, Dilithium, Falcon, and SPHINCS+. We evaluate ten machine-learning models under synthetic and hybrid settings and introduce theDetection Efficiency–Resource (DER)metric to capture accuracy–cost trade-offs. LightGBM attains perfect detection with high DER while training substantially faster than CatBoost; non-boosted models close the classical–quantum gap as data scales from 100K to 200K, though SPHINCS+-based vectors remain challenging. Tunnel zones amplify risk, underscoring the value of zone-aware features. PQ-V2X is, to our knowledge, the first V2X dataset to combine NIST PQC traces, hybrid threats, mobility, and resource-aware benchmarking; data and code are released to enable reproducible, quantum-resilient IDS research.

The security of Vehicle-to-Everything (V2X) networks is fundamental to the realization of next-generation intelligent transportation systems. However, the dynamic nature of V2X environments introduces critical challenges in ensuring robust Intrusion Detection Systems (IDS), particularly concerning false alarm rates, adversarial attacks, computational complexity, and real-world deployment constraints. Traditional centralized machine learning-based IDS suffer from high computation costs, privacy risks, bandwidth constraints, and scalability limitations, making them impractical for real-time, distributed vehicular networks. To address these gaps, this paper provides a comprehensive and structured survey of IDS methodologies in V2X security, focusing on Federated Learning (FL) and Edge AI for privacy-preserving and scalable IDS solutions. Unlike prior works, we systematically analyze and benchmark intrusion detection datasets, highlighting limitations in detecting zero-day attacks and exploring the need for hybrid datasets that integrate real-world vehicular data with adversarial attack scenarios. Furthermore, we investigate the adversarial robustness of ML-based IDS, analyzing AI-based evasion techniques, data poisoning threats, and misbehavior detection challenges. A key novelty of this work lies in the detailed examination of computational complexities in IDS deployment, including sensor fusion methods, noise reduction techniques, and false alarm mitigation strategies, which are often overlooked in previous surveys. We also explore deep learning-based IDS, providing a comparative evaluation of simulated versus real-world performance. Additionally, we present an in-depth discussion on post-quantum cryptographic techniques and blockchain integration for enhancing security in Federated Learning-based IDS. This survey bridges the gap between theoretical IDS models and real-world V2X deployment, addressing key constraints such as energy efficiency, communication overhead, and scalability in resource-constrained vehicular networks. By studying the state-of-the-art methodologies, identifying critical research gaps, and proposing practical advancements, this paper serves as a definitive resource for researchers,and industry professionals, guiding the development of robust, adaptive, and privacy-preserving IDS solutions for next-generation autonomous and connected vehicles (CAVs).

Spiking Neural Networks having biological plausible architecture are considered to be more suitable for energy efficient hardware implementation. When it comes to realize the hardware implementation of a large-scale Neural network for mobile applications, area and power consumption constraints become more critical. Optimizing Spiking neural network, constituting of neuron and synapse circuits, for area and power is essential. In this paper we present a more optimized version of Synapse and neuron circuits. We propose an analog CMOS implementation of a current multiplier charge injector-based Synapse and neuron circuit. The synapse circuit modulates the input spike rates by a trained weight value and injects an equivalent current. The neuron circuit integrates the injected synaptic current and evokes an output digital spike event. The circuit implementation is done using 65nm process design kit. The proposed circuit implementation exhibits all the temporal characteristics of Spiking neural networks. The circuit implementation has been optimized for area and power consumption and therefore can be easily constituted into a large-scale spiking neural network. Furthermore, the compact circuit implementation can benefit from the high resolution with very less increase in area and power.

In this paper, we propose a novel decentralized channel resource allocation algorithm for V2V communication based on deep multi-agent reinforcement learning. Each vehicle behaves as an independent agent and uses its local observation to select the optimal resource blocks (RBs) from pre-conflgured resource pool (environment). The selected RB is considered optimal if transmission within this RB causes a minimum interference to other ongoing transmissions. We applied an actor-critic reinforcement learning algorithm to let each agent conduct a centralized training and decentralized execution. In centralized training, agents share their actions and local observations through the centralized critic network. While making a decision (choosing the optimal resource blocks), therefore, each agent can estimate the policies of other agents. In decentralized execution, each agent uses its local observation to optimize its local policy independently. Each action taken by an agent in actor network is judged by its private critic network.

The use of multiple channels often increases the capacity of a wireless network, especially, if those channels are orthogonal. However, the challenge lies when we have more nodes than the available orthogonal channels. The 802.11n, 2.4 GHz WLAN has 3 orthogonal channels and 8 partially overlapping channels. These numbers of orthogonal channels put a limitation on the channel usage in a network and thus affect the overall network capacity. To overcome this degradation of network capacity with such limited channel scenario, we must focus on the transmission power of these nodes. In this paper, we describe a smart algorithm with realistic formulation, which divides the complex channel assignment and power optimization problem into two separate solution sets. First solution set solves the channel assignment problem in access points of the 802.11 infrastructure based network utilizing both orthogonal and overlapping channels and the second solution set improves the throughput of the network by optimizing the transmission power of these nodes. We selected optimal channel and transmission power assignment using the algorithm, and then ran simulations on a set of multi-AP WLAN. Experimental results show an improvement of approximately 14% in the throughput of infrastructure based 802.11n WLAN compared to previous work.

With the introduction of IEEE 802.11ah wireless LAN standard, Internet of Things (IoT) is expected to develop more rapidly. IEEE 802.11ah introduces a relay node to extend wireless range with high energy efficiency for a large number of station nodes. This paper presents an efficient method of allocating multiple channels to multiple relay nodes of IEEE 802.11ah network. We propose a formulation for an optimal calculation of mutual exclusive segment angle using wireless link parameters. We present a hierarchical Medium Access Control (MAC) mechanism for efficient management and deployment of relays. It increases wireless range of network, improves the overall throughput by minimizing interference, and effectively conserves station node's energy. We implemented IEEE 802.11ah relay protocol based the hierarchical MAC using ns-3 simulator. Experimental results show that the proposed scheme provides substantial improvement in throughput performance.

Conventional automatic test-pattern generation (ATPG) cannot effectively handle designs employing blocks whose implementation details are either unknown, unavailable, or subject to change. Realization-independent block testing for cores (RIBTEC), a novel ATPG program for such designs, is described, which employs a functional (behavioral) fault model based on a class of nonexhaustive "universal" test sets. Given a circuit's high-level block structure, RIBTEC constructs a universal test set (UTS) for each block from its functional description in such a way that realization independence of the blocks is ensured. Experimental results are presented for representative datapath circuits, which demonstrate that RIBTEC achieves very high fault coverage and an exceptionally high level of realization independence. We also show that RIBTEC can be applied to designs containing a class of small intellectual property (IP) circuits (cores).

Predesigned blocks called intellectual property (IP) cores are increasingly used for complex system-on-a-chip (SoC) designs. The implementation details of IP cores are often unknown or unavailable, so delay testing of such designs is difficult. We propose a method that can test paths traversing both IP cores and user-defined blocks, an increasingly important but little-studied problem. It models representative paths in IP circuits using an efficient form of binary decision diagram (BDD) and generates test vectors from the BDD model. We also present a partitioning technique, which reduces the BDD size by orders of magnitude and makes the proposed method practical for large designs. Experimental results are presented that show that it robustly tests selected paths without using extra logic and, at the same time, protects the intellectual contents of IP cores.

Delay testing of designs that contain intellectual property (IF) cores is challenging. We propose a method that can test paths traversing both IP cores and user-defined blocks. It employs a highly efficient BDD-based path modeling method and an associated ATPG technique. Experimental results show that it robustly tests selected paths without using extra logic, and, at the same time, protects the intellectual property.

Conventional methods cannot effectively verify path delays of designs employing IP circuits (cores) whose implementation details are hidden. A delay fault ATPG method for such designs is proposed that employs a scan technique called selectively transparent scan (STS). Experimental results are presented which show that the STS method can robustly test paths of a specified delay range in core-based circuits, and substantially reduce test length.

Conventional ATPG cannot effectively handle designs employing IP circuits (cores) whose implementation details are either unknown, unavailable, or subject to change. A new ATPG program RIBTEC for such designs is described that employs a functional (behavioral) fault model based on a class of non-exhaustive "universal" test sets. Given a circuit's high-level block structure, RIBTEC constructs a universal test set for each block from its functional description in such a way that realization-independence of the blocks is ensured. Experimental results are presented for representative datapath circuits, which show that RIBTEC achieves very high fault coverage and an exceptionally high level of realization independence.