The chase for high yield designs can effectively reduce chip manufacturing costs, making yield optimization a crucial problem in the IC community. However, the timeconsuming Monte Carlo simulations required by yield analysis hinder the traditional yield optimization methods from applying to the efficient analog circuit design flow, especially in high-dimensional design spaces. In this paper, we propose a high-dimensional yield optimization method via Monte Carlo tree search and self-regressive auto-encoder promoted subspace decomposed Gaussian process. To mitigate the common issue of over-exploration in high-dimensional optimization, a Monte Carlo tree is adopted to quickly identify promising local regions within the design space. The optimization in the selected region is realized by Bayesian optimization. To further accelerate the convergence speed of local optimization, a self-regressive autoencoder is proposed to adaptively learn for each performance metric an embedded linear subspace with dimensionality much smaller than the original design space. A specific subspace decomposed Gaussian process is constructed to model the yield variation based on the low-dimensional features of observed design parameters. A message passing algorithm is used to efficiently maximize the acquisition function, which obtains the next candidate design in intersected subspaces. Compared with the state-of-the-art methods, the proposed method achieves 2:20× – 3:99× speedup in simulation cost and 5:22×–14:33× speedup in time cost when tested in three real circuit designs.

This paper introduces Atelier, a large language model (LLM)-based framework for analog circuit design to address the issues of data scarcity and the substantial domain-specific knowledge required in this field. Atelier integrates general-purpose LLMs with a high-quality, compact knowledge base to fulfill the considerable knowledge requirements of analog circuit design, obviating the need for extensive domain-specific training or fine-tuning. The knowledge base is meticulously curated to be task-oriented and encapsulates critical information from pertinent literature within user-defined templates, leveraging the LLMs’ capabilities in text comprehension and summarization. The framework comprises several LLM agents, structured in a graph-of-thoughts architecture, with each agent specialized in a distinct task in analog circuit design, including circuit analysis, topology selection, topology modification, parameter tuning, and design decision. This collaborative multi-agent system, enriched with access to the compact knowledge base and advanced mechanisms such as self-reflection, backtracking, and tool integration, automates the analog circuit design process. It significantly enhances design quality and efficiency while ensuring interpretability. Experimental results highlight Atelier’s superiority over state-of-the-art black-box methods, general-purpose LLMs, and LLM-based methods, demonstrating notable improvements in success rates, design quality, and runtime.

Robust analog circuit design is becoming increasingly challenging due to process, voltage, and temperature (PVT) variations at advanced technology nodes. In this article, we formulate analog circuit synthesis as a robust optimization problem, and propose a Contextual Robust OptimiZAtion (CROZA) method for variation-aware analog circuit design. The proposed method uses Contextual Gaussian process to model both the design parameters and perturbation parameters, and a hybrid strategy of adversarially robust optimization and stochastically perturbed robust optimization to find robust solutions. Compared to state-of-the-art methods, our proposed approach achieves significant simulation and runtime speedups while delivering superior optimization results.

As semiconductor technology node advances, the number of parameters in the modern device compact model increases drastically. Manual extraction of these model parameters becomes not only tedious but also impossible, and the automatic method is strongly desired. Traditional black-box optimization suffers from poor scalability due to the curse of dimensionality, while deep learning–based methods typically require large amounts of training data. To address these challenges, we propose CDRPE: a combined deep learning and self-attention enhanced reinforcement learning framework for automatically extracting a large set of DCM parameters across multiple electrical characteristics. The framework leverages a pre-trained multilayer perceptron to initialize core parameters, incorporates device physics knowledge to guide the search, and employs a self-attention–enhanced RL agent for efficient exploration in high-dimensional parameter spaces. Experimental results on BSIM4, BSIMSOI, and BSIMCMG demonstrate that CDRPE can automatically extract 100 parameters with root-mean-square error below 5% relative to TCAD and silicon data. Compared with existing methods, the proposed framework achieves a 7.7x speed up. Moreover, the generated models show good convergence in both digital and analog circuit simulations, exhibiting the potential of this framework for future practical applications.

Numeric optimization methods are widely utilized to tackle complex analog circuit sizing problems, where the challenges include expensive simulations, non-linearity, and high parameter dimensionality. However, the diverse characteristics exhibited by different circuits result in varied optimization landscapes, making it difficult to identify a single algorithm that consistently outperforms others across all problems. In this paper, we introduce a multi-algorithm interworking optimization framework, which achieves optimization superadditivity based on a pool of member algorithms and a powerful algorithm-interworking protocol. We propose a computing resource reallocation method, which employs multitask Gaussian process regression and portfolio optimization techniques, leading to flexible and prudent online adaption of member algorithms. To efficiently utilize the computing resources for local exploitation, an evaluation data broadcast strategy enables cooperativeness across member algorithms. Besides, algorithms with different modeling overheads are integrated time-adaptively via an asynchronous parallelization mechanism. Comparative experiments against state-of-the-art algorithmcombining tools and optimization algorithms demonstrate the superiority of the proposed optimization framework.

The parameterizable and synthesizable RISC-V processors enable the automatic generation of customized CPU cores through EDA tools. However, current methods often explore the extensive design space with significant model errors while neglecting design constraints, which are critical for practical implementations. To address these limitations, we propose a Self-Review Bayesian Optimization method (SRBO). This method integrates a teacher-student paradigm within a local Bayesian optimization framework to reduce model errors and enhance exploration efficiency. Additionally, it employs deep ensembles for effective constraint handling. Experimental results demonstrate that our approach outperforms state-of-the-art methods within a limited time budget, significantly enhancing exploration efficiency.

This paper presents INTO-OA, an interpretable topology optimization method for operational amplifiers (op-amps). We propose a Bayesian optimization-based approach to effectively explore the high-dimensional, discrete topology design space of op-amps. Our method integrates a Gaussian process surrogate model with the Weisfeiler-Lehman graph kernel to extract structural features from a dedicated circuit graph representation. It also employs a candidate generation strategy that combines random sampling with mutation to balance global exploration and local exploitation. Additionally, INTO-OA enhances interpretability by assessing the impact of circuit structures on performance, providing designers with valuable insights into generated topologies and enabling the interpretable refinement of existing designs. Experimental results demonstrate that INTO-OA achieves higher success rates, a 1.84× to 19.10x improvement in op-amp performance, and a 3.20x to 14.33× increase in topology optimization efficiency compared to state-of-the-art methods.

Thermal issues are critical in 2.5D/3D IC design, and liquid cooling provides an effective solution for heat dissipation. Widely used compact thermal models (CTMs) convert chips into circuit networks for fast thermal simulations. However, current matrix-solving acceleration methods for CTM-derived circuits are inadequate for high-speed iterative transient thermal analysis of large-scale liquid-cooled 2.5D/3D ICs during design optimization. In contrast, the random walk method can provide fast solutions for local nodes in large-scale circuit networks, but it is not applicable to the circuit networks of the CTMs with liquid cooling. In this paper, we propose LCTMwalk, a novel GPU-accelerated random walk method for transient thermal analysis of liquid-cooled 2.5D/3D ICs. To enable random walks on the liquid-cooled CTM-derived circuit network, we replace the voltage-controlled current source model with the diode model. Additionally, we improve the transient analysis by using a time-backward random walk with time-domain path reuse, accelerating the solution of temperature at local circuit nodes. Experimental results show LCTMwalk can solve million-scale cases in only 500 ms, and achieves a 14-22× speedup compared to the state-of-the-art alternating direction implicit (ADI) method with GPU. Besides, LCTMwalk exhibits good generalizability and can be applied to various 2.5D/3D IC structures with high accuracy (error<1 K compared to 3D-ICE).

For highly integrated, thermally constrained chiplets, the design process requires iterative shape optimization, making rapid thermal simulation across varying geometries critically important. Existing deterministic approaches, such as COMSOL and HotSpot require solving large-scale linear systems, incurring expensive computational costs. Stochastic methods suffer from slow convergence, demanding excessive resources for high-precision results. Current neural network (NN)-based methods necessitate retraining upon geometry modifications, limiting adaptability. Meanwhile, neural networks suffer from the absence of provable error bounds, introducing three fundamental risks in practical deployment. We enable the fast solution of heat equations for varying geometries and propose a novel solver that integrates operator learning with stochastic methods. By employing diffeomorphic mapping, our approach addresses the challenge of operator networks in handling shape variations. Furthermore, the network’s predictions guide the stochastic method for variance reduction, which extremely accelerates the traditional stochastic method, while the stochastic results provide error guarantees and corrections for the neural network’s outputs. Extensive experiments show that we achieve a speedup of 10.69-23.04× over commercial field solver COMSOL and a speedup of 5.20-11.87× over the traditional stochastic methods.

Yield analysis has grown in significance with the increasing integration of SRAM arrays. The post-layout simulation introduces strong inter-column correlations in SRAM caused by parasitic parameters, thereby complicating yield analysis. However, most existing methods only consider the pre-layout simulation of SRAM circuits. In this paper, we present BAGNet: a boundary-aware Graph Neural Network (GNN) for SRAM yield analysis in post-layout simulation. We introduce a GNN module that learns the graph representations of SRAM arrays while generating feature vectors. We then construct an accurate surrogate model by the Multilayer Perceptron (MLP) to provide predictions for circuit performances. Given that delineating failure boundaries is vital for yield estimation, we propose an innovative nonlinear mapping strategy and an adaptive iterative strategy integrated with BAGNet, thus endowing our model with boundary-aware capability. After the model is built, we employ the importance sampling (IS) method on our surrogate model to deliver efficient and accurate yield estimation without time-consuming circuit simulations. Experimental results demonstrate that BAGNet outperforms the state-of-the-art method with 1.823.52x speedup, without losing accuracy.

Modern processor microarchitectures face increasing complexity, leading to larger search spaces and lengthy design-to-silicon validation flows. While reusing design knowledge across architectures offers potential efficiency gains, the common practice remains specific-architecture search due to inherent discrepancies in power, performance, and area (PPA) metrics between designs. We propose an attention-based microarchitecture search framework for effective cross-architecture knowledge transfer. Our approach propose a cross-attention network to capture interdependencies between microarchitectural topology and design tool configurations, enabling knowledge adaptation across architectures with minimal fine-tuning. Additionally, we complement it with an uncertainty-guided optimization strategy that efficiently navigates search based on specific user preferences. Experimental results demonstrate our approach outperforms previous methods with 68.16% higher hypervolume indicators and 3.85× speed-up of time in reaching the same hypervolume. Furthermore, our approach successfully discovers design points that meet user-specified PPA targets that state-of-the-art (SOTA) methods failed to identify. Our code is publicly available at https://github.com/MarsH3107/ICAN, enabling broader adoption and encouraging further research in transferable processor design optimization.

With the rapid increase of the transistor number in VLSI, rapidly rising power density and temperatures make heat dissipation a major challenge in IC design and manufacturing. However, conventional deterministic thermal analysis methods have difficulties in obtaining local temperature solutions efficiently, and the existing stochastic method is inaccurate when dealing with thermal analysis problems involving Robin boundary conditions (BCs). In this article, a highly parallelized path integral random walk (PIRW) solver is innovatively proposed for steady-state thermal analysis with mixed BCs, especially Robin BCs. The rigorous calculation of the local time and the Feynman-Kac functional$\hat {e}_{c}(t)$are adopted to accurately handle Neumann and Robin BCs for the first time. Furthermore, based on the PIRW, we propose an accurate and microsecond-level precalculation PIRW (pPIRW) predictor, which precalculates time-consuming random walks, obtains temperatures by simple vector multiplication, and therefore is suitable for proactive thermal management. The pPIRW essentially calculates a partial inverse of large-scale matrices constructed from the finite difference-based compact thermal models (CTMs). Experimental results show that compared with 3D-ICE, the PIRW solver maintains high accuracy with a negligible error within$0.5~^{\circ }$C, achieves$136\times $–$209\times $speedup and$8.53\times $–$11.1\times $storage space reduction with all three kinds of BCs, and decreases to$1\times $–$1.53\times $speedup for lacking the absorbing Dirichlet boundary. The pPIRW further has speed improvement of 2.5e$4\times $–6.7e$6\times $and memory reduction of$36.6\times $–$42.5\times $over PIRW without loss of accuracy. Integrated within a thermal management strategy, the pPIRW predictor can eliminate all thermal conflicts while maintaining the highest working frequency. Meanwhile, pPIRW achieves$29.2\times $speedup and$634\times $memory reduction over the CTM during the offline precalculation stage.

Bayesian optimization (BO) is more efficient in automatically synthesizing operational amplifier (opamp) topologies compared to conventional methods. However, the design space for behavior-level opamp topologies involves numerous connections that are difficult to comprehend, and evaluating each topology incurs substantial computational costs. To tackle these challenges, this brief introduces ATOM, an automatic opamp topology synthesis framework. We construct a concise design space for behavior-level opamp topologies, consisting of topologies that designers can easily understand. We propose an opamp topology optimization method that incorporates freeze-thaw BO. This method efficiently explores the design space and expedites the evaluation process. Experimental studies demonstrate that ATOM outperforms state-of-the-art topology synthesis methods in terms of success rate and optimization results while reducing the number of required simulations by up to 8.15 times. The source code for ATOM is available athttps://github.com/Jinyi-Shen/ATOM.

The synthesizable and parameterizable RISC-V microarchitecture, combined with multiobjective optimization-based design space exploration (DSE), facilitates agile adaptation to various microprocessor designs for customized applications. However, to enhance design quality, DSE must consider both architecture parameters and EDA tool parameters, resulting in exponentially increased optimization complexity with the dimensionality of parameters. Exhaustively exploring the whole design space is impossible. Additionally, due to the time-consuming nature of microprocessor simulation, minimizing the number of simulations is imperative. Addressing these challenges, we propose asynchronous parallel Pareto set learning for microarchitecture DSE (APPLE-DSE). APPLE-DSE utilizes the Pareto set learning (PSL) technique to obtain an approximate Pareto front with a “light-weight” evaluation. PSL captures the structural characteristics of the Pareto set (PS) guided by the surrogate models, enabling it to explore any tradeoff area in the approximate PS. Employing the probabilistic reparameterization (PR) technique, APPLE-DSE adapts PSL to handle discrete variables. Furthermore, APPLE-DSE incorporates a simulation time-aware asynchronous parallel scheduling strategy to further enhance optimization efficiency. Experimental results show that APPLE-DSE achieves a maximum improvement of 16.81% in hypervolume within the same time budget and a$127.73\times $speedup in algorithm run time per iteration compared to state-of-the-art methods.

Optimizing multiple competitive black-box objectives with tight constraints poses a common challenge in analog circuit design. Multiobjective Bayesian optimization (MOBO) is a sample-efficient approach to identify the optimal tradeoffs, namely, the Pareto front (PF). However, existing MOBO methods exhibit limitations in handling high-dimensional design space, large sample budgets, many objectives and tight constraints. This article introduces VTSMOC, a sample-efficient and computationally lightweight approach for addressing high-dimensional constrained multiobjective optimization problems. VTSMOC decomposes the design space into Voronoi cells, dynamically constructing a hierarchical Voronoi tree through clustering observations with dominance relationships. Promising leaf nodes in the Voronoi tree are pinpointed by traversing the tree with gradient bandit. The diversity of PF is ensured by parallel sampling within different promising cells, selected using a diffusive strategy. We also propose the expected PF improvement (EPFI) and probability of PF improvement (PPFI) acquisition functions to facilitate the PF efficiently along the radial direction of PF surface. Compared to state-of-the-art methods, VTSMOC achieves significant improvements in both sample and computational efficiency.

Design automation of complex analog circuits (CAC) with multiple sub-blocks is challenging mainly due to large design search space, uncertain intermediate subgoal creation, and lengthy CAC simulation runtime. In this work, we propose a hierarchical and heterogeneous integration framework as a fully automated and time-efficient CAC design optimization solution. In Particularly, we (i) decompose CAC into two levels hierarchically and for the first time introduce hierarchical RL agents with hindsight and subgoal testing to automate the subgoal creation between these two levels. The subgoal converges to the optimal value through algorithm interactions. (ii) We enable high-level design space dimensionality reduction, minimize CAC simulation runs through a buffer hold, and employ low-level sub-block execution parallelization to reduce overall runtime. (iii) We construct a heterogeneous integration of different RL algorithms and black-box optimization algorithms in hierarchy to further boost the speed by benefiting both from the hierarchical structure and the advantages of each different algorithm. Experiments on four CAC topologies demonstrate that this framework achieves a maximum of 11.4× speed up compared to existing methods at the desired figure-of-merit. This work opens up a time efficient design automation route for complex analog circuits and systems.

The optimization of RISC-V designs, encompassing both microarchitecture and CAD tool parameters, is a great challenge due to an extensive and high-dimensional search space. Conventional optimization methods, such as case-specific approaches and black-box optimization approaches, often fall short of addressing the diverse and complex nature of RISC-V designs. To achieve optimal results across various RISC-V designs, we propose the cooperative optimization framework (COF) that integrates multiple black-box optimizers, each specializing in different optimization problems. The COF introduces the landscape knowledge exchange mechanism (LKEM) to direct the optimizers to share their knowledge of the optimization problem. Moreover, the COF employs the dynamic computational resource allocation (DCRA) strategies to dynamically allocate computational resources to the optimizers. The DCRA strategies are guided by the optimizer efficiency evaluation (OEE) mechanism and a time series forecasting (TSF) model. The OEE provides real-time performance evaluations. The TSF model forecasts the optimization progress made by the optimizers, given the allocated computational resources. In our experiments, the COF reduced the cycle per instruction (CPI) of the Berkeley out-of-order machine (BOOM) by 15.36% and the power of Rocket-Chip by 12.84% without constraint violation compared to the respective initial designs.

The escalated intricacy of analog circuits, compounded by the high-dimensional nature of the design space, introduces complexities in optimizing circuit performance. Since the evaluation cost, often through circuit simulation, is resource-intensive and time-consuming, it is crucial to obtain a feasible design with a decent Figure of Merit (FOM) value within a limited simulation budget. In this study, we conduct an in-depth review and analysis of cutting-edge exploration and exploitation techniques developed to address the intricacies encountered in analog circuit design automation. Moreover, to enable algorithmic comparisons and advance the state of the field, we provide benchmarks encompassing analog circuit netlists with high-dimensional design variables, which empower researchers to rigorously assess and refine their optimization algorithms, leading to enhanced efficacy and novel developments.

For analog circuit sizing, constrained multi-objective optimization is an important and practical problem. With the popularity of multi-core machines and cloud computing, parallel/batch computing can significantly improve the efficiency of optimization algorithms. In this paper, we propose an Asynchronous Batch Constrained Multi-Objective Bayesian Optimization algorithm (ABCMOBO). Since the performances below the specifications are worthless, we adopt a dynamic reference point selection on the expected hypervolume improvement acquisition function for constraint handling. To save the time of waiting for all the simulations in the same batch to complete, ABCMOBO asynchronously evaluates the next candidate point if there is an idle worker. The experimental results quantitatively demonstrate that our proposed algorithms can reach 3.49 ~ $8.18 \times$ speed-up with comparable optimization results compared to the state-of-the-art asynchronous/synchronous batch multi-objective optimization methods.

This study presents a novel high-dimensional multi-objective optimization method via adaptive gradient-based subspace sampling for analog circuit sizing. To handle constrained multi-objective optimization, we exploit promising regions from a non-crowded Pareto front, with lightweight Bayesian optimization (BO) based on a novel approximate constrained expected hypervolume improvement. This lightweight BO is computational efficient with constant complexity concerning simulation numbers. To tackle high-dimensional challenges, we reduce the effective dimensionality around promising regions by sampling candidates in an adaptive subspace. The subspace is constructed with gradients and previous success steps with their significance decaying over iterations. The gradients are approximated by sparse regression without additional simulations. The experiments on synthetic benchmarks and analog circuits illustrate advantages of the proposed method over Bayesian and evolutionary baselines.

Automated analog circuit design migration significantly alleviates the burden on designers in circuit sizing under various operating conditions. Conventional methods model the migration problem as black-box optimization, requiring excessive iterations of costly simulations to converge. Reinforcement learning exhibits significant promise in transfer learning, as it enables the generation of circuits that fulfill specifications efficiently. The paper proposes a novel value decomposition-based multi-agent reinforcement learning framework, aiming to model complex analog circuits and eliminate the need for manually defined specifications of sub-circuits for new operating conditions. Additionally, it incorporates domain randomization techniques to efficiently generate circuits that meet unforeseen scenarios with minimal simulations. Experiment demonstrates that our algorithm can efficiently generate circuits meeting specifications under new operating conditions in few number of steps, outperforming state-of-the-art methods.

We propose a novel scalable Bayesian optimization method with truncated subspace sampling (tSS-BO) to tackle high-dimensional optimization challenges for large-scale analog circuit sizing. To address the high-dimensional challenges, we propose subspace sampling subject to a truncated Gaussian distribution. This approach limits the effective sampling dimensionality down to a constant upper bound, independent of the original dimensionality, leading to a significant reduction in complexity associated with the curse of dimensionality. The distribution covariance is iteratively updated using a truncated flow, where approximate gradients and center steps are integrated with decaying prior subspace features. We introduce gradient sketching and local Gaussian process (GP) models to approximate gradients without additional simulations to mitigate systematic errors. To enhance efficiency and ensure compatibility with constraints, we utilize local GP models for the selection of promising candidates, avoiding the cost of acquisition function optimization. The proposed tSS-BO method exhibits clear advantages over state-of-the-art methods in experimental comparisons. In synthetic benchmark functions, the tSS-BO method achieves up to$4.93\times$evaluation speedups and a remarkable over$30\times$algorithm complexity reduction compared to the Bayesian baseline. In real-world analog circuits, our method achieves up to$2\times$speedups in simulation number and runtime.

We propose a pyramid scene parsing network (PSPN) with skip-connection architecture to effectively utilize physical information that characterizes IR drop distribution, including current source locations, via locations, and asymmetric topological connections, achieving highly accurate IR drop prediction for power delivery networks (PDN) of varying scales, even with a limited dataset. Skip-connection architecture preserves the positional information of current sources, which often correlates with large IR drop, facilitating the identification of hotspots. We incorporate via locations into the model to effectively describe the topological connection distance between voltage sources and different nodes in the multi-layer PDN, while the traditional method only considers the horizontal distance between nodes and voltage sources, which is invalid for prediction. To capture asymmetric connection features within the PDN efficiently, we introduce a shape-adaptive convolutional kernel to solve the problem of inadequate extraction of feature information in a traditional method. Finally, we propose a loss function with Kirchhoff's law constraints to ensure the model's prediction aligns with the electrical characteristics of the circuit, which can't be guaranteed by traditional machine learning-based methods only taking the prediction accuracy into consideration. Our results, based on training with only 100 synthetic circuits, demonstrate the superiority of our method over the state-of-the-art prediction technique. Across evaluations on 10 real circuits, our approach consistently delivers a 50 % improvement in precision.

Recent advances in machine learning (ML) for automating analog circuit synthesis have been significant, yet challenges remain. A critical gap is the lack of a standardized evaluation framework, compounded by various process design kits (PDKs), simulation tools, and a limited variety of circuit topologies. These factors hinder direct comparisons and the validation of algorithms. To address these shortcomings, we introduced AnalogGym, an open-source testing suite designed to provide fair and comprehensive evaluations. AnalogGym includes 30 circuit topologies in five categories: sensing front ends, voltage references, low dropout regulators, amplifiers, and phase-locked loops. It supports several technology nodes for academic and commercial applications and is compatible with commercial simulators such as Cadence Spectre, Synopsys HSPICE, and the open-source simulator Ngspice. AnalogGym standardizes the assessment of ML algorithms in analog circuit synthesis and promotes reproducibility with its open datasets and detailed benchmark specifications. AnalogGym's user-friendly design allows researchers to easily adapt it for robust, transparent comparisons of state-of-the-art methods, while also exposing them to real-world industrial design challenges, enhancing the practical relevance of their work. Additionally, we have conducted a comprehensive comparison study of various analog sizing methods on AnalogGym, highlighting the capabilities and advantages of different approaches. AnalogGym is available in the GitHub repository1. The documentations are also available at2.

Current state-of-the-art (SOTA) analog circuit sizing methods predominantly rely on derivative-free algorithms. However, these methods struggle with sample efficiency due to the lack of derivative information, acting as a bottleneck for further advancements. In contrast, classic sensitivity analysis computes partial derivatives of circuit performance with respect to design parameters, enabling efficient first-order optimization. Yet, sensitivity-driven analog sizing has seen limited use due to: 1) accumulated numerical errors from nonlinear devices, and 2) the complex, non-convex nature of circuit optimization problems, which makes local search methods like gradient descent ineffective for global optimization. To address these challenges, this paper equips SOTA analog sizing algorithms with derivative awareness and proposes DarBO, a Derivative-aware Bayesian Optimization method. DarBO uses derivatives from error-suppressed adjoint sensitivity analysis to improve Gaussian process posteriors in local optimization, enhancing convergence with fewer circuit simulations. For global exploration, DarBO adapts a derivative-aware Gaussian mixture model (d-GMM) for region partitioning and a gradient-driven Monte Carlo tree search (d-MCTS) for subregion selection. By bridging classic sensitivity-driven analog sizing with SOTA Bayesian optimization algorithms, DarBO offers an efficient and robust solution for analog circuit sizing. Experimental results show that DarBO achieves up to 5.0 × acceleration in terms of the number of circuit simulations compared to existing first-order and derivative-free optimization methods.

Bayesian optimization (BO) is a well-established methodology for optimizing costly black-box functions. However, the sparse observations in the high-dimensional search space pose challenges in constructing reliable Gaussian Process (GP) models, which leads to blind exploration of the search space. We propose a novel Voronoi Graph Traversing (VGT) algorithm to extend BO to ultra high-dimensional problems. VGT employs a Voronoi diagram to mesh the design space and transform it into an undirected Voronoi graph. VGT explores the search space by iteratively performing path selection, promising cell sampling, and graph expansion operations. We introduce a UCB-based global traversal strategy to select the path towards promising Voronoi cells. Then we perform local BO within the promising cell and train local GP with a neighboring subset. The intrinsic geometric boundaries and adjacency of the Voronoi graph assist in fine-tuning the trajectory of local BO sampling. We also present a subspace enhancement approach for the intrinsic low-dimensional problems. Experimental results, including both synthetic benchmarks and real-world applications, demonstrate the proposed approach’s state-of-the-art performance for tackling ultra high-dimensional problems ranging from hundreds to one thousand dimensions.

Despite the effort of analog circuit design automation, currently complex analog circuit design still requires extensive manual iterations, making it labor intensive and time-consuming. Recently, reinforcement learning (RL) algorithms have been demonstrated successfully for the analog circuit design optimization. However, a robust and highly efficient RL method to design analog circuits with complex design space has not been fully explored yet. In this work, inspired by multiagent planning theory as well as human expert design practice, we propose a multiagent based RL (MA-RL) framework to tackle this issue. Particularly, we (i) partition the complex analog circuits into several sub-blocks based on topology information and effectively reduce the complexity of design search space; (ii) leverage MA-RL for the circuit optimization, where each agent corresponds to a single sub-block, and the interactions between agents delicately mimic the best design tradeoffs between circuit sub-blocks by human experts; (iii) introduce and compare three different multiagent RL algorithms and corresponding frameworks to demonstrate the effectiveness of the MA-RL method. (iv) employing twin-delayed techniques and proximal policy to further boost training stability and accomplish higher performances. (v) The impacts of different reward function definitions as well as different state settings of MA-RL agents are investigated to further improve the robustness of this framework. (vi) Experiments on three different complex analog circuit topologies (GBA, DLL and SAR ADC) and knowledge transfers between two technology nodes are demonstrated. It’s shown that MA-RL framework can achieve the best FoM for complex analog circuits’ design. This work shines the light for future large scale analog circuit system design automation.

Dummy filling is widely applied to significantly improve the planarity of topographic patterns for the chemical mechanical polishing (CMP) process in VLSI manufacturing. In the dummy filling flow, dummy synthesis works as the key step to adjust the post- CMP profile height. However, existing dummy synthesis optimization approaches usually fail to balance the filling quality and efficiency. This article proposes a novel model-based dummy filling synthesis framework NeurFill, integrated with multiple starting points-sequential quadratic programming (MSP-SQP) optimization solver. Inside this framework, a full-chip CMP simulator is first migrated to the neural network, achieving$8134\times $speedup on gradient calculation by backward propagation. Entrenched in the CMP neural network models, we further implement an improved version of NeurFill (pNeurFill) to alleviate the post- CMP height variation caused by dummy perimeter. After each iteration of dummy density optimization, an additional perimeter adjustment based on a given candidate dummy pattern set is applied to search for the optimal perimeter fill amount. The experimental results show that the proposed NeurFill outperforms existing rule- and model-based methods. The extra perimeter adjustment strategy in pNeurFill can achieve an average 66.97Å decreasing in height variation and 8.92% quality improvement compared to NeurFill. This will provide guidance for DFM so as to increase IC chip yield.

In this article, we propose a novel batch Bayesian and Gaussian process enhanced subspace derivative free optimization (DFO) method to solve high-dimensional and simulation-expensive analog circuit optimization problems. The existing optimization methods, such as Bayesian optimization and trust region-based DFO, suffer from under-fitting surrogate models in high-dimensional problems, which leads to inefficient optimization and suboptimal solutions. To address this issue, we propose a novel approach that integrates a batch Bayesian querying strategy for exploring the global design space and a Gaussian process (GP) enhanced subspace DFO method for exploiting promising regions in effective low-dimensional subspace. The GP is used to approximate the gradient pattern for subspace establishment, significantly enhancing the simulation efficiency. The selection of promising regions is based on an innovative region acquisition function that estimates the weighted local expected improvement. The effectiveness of the proposed method is demonstrated on real-life analog circuits, achieving${2.05\times - 17.65\times }$simulation number speedup and${1.37\times - 16.11\times }$runtime speedup compared with the state-of-the-art optimization methods.

Exploring the design space of RISC-V processors faces significant challenges due to the vastness of the high-dimensional design space and the associated expensive simulation costs. This work proposes a region of interest (ROI)-driven method, which focuses on the promising ROIs to reduce the over-exploration on the huge design space and improve the optimization efficiency. A tree structure based on self-organizing map (SOM) networks is proposed to partition the design space into ROIs. To reduce the high dimensionality of design space, a variable selection technique based on a sensitivity matrix is developed to prune unimportant design parameters and efficiently hit the optimum inside the ROIs. Moreover, an asynchronous parallel strategy is employed to further save the time taken by simulations. Experimental results demonstrate the superiority of our proposed method, achieving improvements of up to 43.82% in performance, 33.20% in power consumption, and 11.41% in area compared to state-of-the-art methods.

Bayesian optimization (BO) is an efficient global optimization method for expensive black-box functions, but the expansion for high-dimensional problems and large sample budgets still remains a severe challenge. In order to extend BO for large-scale analog circuit synthesis, a novel computationally efficient parallel BO method, D 3 PBO, is proposed for high-dimensional problems in this work. We introduce the dynamic domain decomposition method based on maximum variance between clusters. The search space is decomposed into subdomains progressively to limit the maximal number of observations in each domain. The promising domain is explored by multi-trust region-based batch BO with the local Gaussian process (GP) model. As the domain decomposition progresses, the basin-shaped domain is identified using a GP-assisted quadratic regression method and exploited by the local search method BOBYQA to achieve a faster convergence rate. The time complexity of D 3 PBO is constant for each iteration. Experiments demonstrate that D 3 PBO obtains better results with significantly less runtime consumption compared to state-of-the-art methods. For the circuit optimization experiments, D 3 PBO achieves up to 10× runtime speedup compared to TuRBO with better solutions.

A constrained Voronoi tree-based domain decomposition method for high-dimensional Bayesian optimization is proposed to solve large scale analog circuit synthesis problems, which can be formulated as high-dimensional heterogeneous black-box optimization. Hierarchical Voronoi tree progressively breaks down the design space into partitions with implicit performance boundaries such that promising regions are efficiently explored. Fast exploitation is ensured in Voronoi nest via local Bayesian optimization with a few observations. A slice-enhanced Gibbs sampling method is proposed to sample acquisition function cMES in irregular polyhedrons with design constraints. Compared with state-of-the-art methods, cVTS achieves significant speed up without loss of accuracy.

Device sizing is a challenging problem for analog circuit design. Traditional methods depend on domain knowledge and intensive simulations to search for feasible parameters. Recent studies apply the Bayesian optimization (BO) and a Gaussian process (GP) model in analog circuit synthesis to improve efficiency. The BO framework automatically selects the parameter candidates by inferring the surrogate GP model. However, naive BO employs a sequential updating strategy which is inefficient in a multicore environment. Besides, the widely used GP model requires costly high fidelity data, which are obtained from fine simulations. In this article, we propose a constrained batch BO approach with a multifidelity (MF) model to solve the above difficulties. The batch BO exploits parallel computing and selects promising parameters by multiple acquisition function ensemble. In addition, the MF GP model adapts the low fidelity data obtained from coarse simulations. Specifically, the proposed method incorporates information gain in a weighted clustering algorithm to refine the parameter candidates. As a result, the proposed method maintains the candidates’ quality and diversity, which speeds up the optimization convergence. In the experiments, we demonstrate the efficiency of the proposed approach on three real-world circuits. The results show that our approach reduces the simulation costs by at least 54.6% compared to the state-of-the-art baselines.

Analog circuits are characterized by various circuit performances obtained from multiple testbenches which need to be simulated independently. In this paper, we propose an efficient Bayesian optimization approach for multi-testbench analog circuit design. Predictive Entropy Search with Constraints (PESC) is applied for selecting the suitable testbench to simulate, and time-weighted PESC (wPESC) is also proposed considering different analysis time. Furthermore, the Feasibility Expected Improvement (FEI) acquisition function for constraints and solving a multi-modal optimal problem of FEI are proposed to improve the efficiency of exploring feasible regions. The proposed approach can gain$2.{7}\sim 3.8\times$speedup compared with the state-of-the-art method, and achieve better optimization results.

In this paper, we propose an efficient batch Bayesian optimization algorithm for analog circuit synthesis based on the multi-points selection criterion. Simplex evolution operator and Niching Migratory Multi-Swarm Optimizer (NMMSO) are used to generate candidates. The multi-point selection criterion is adopted to select multiple points from the candidates for parallel evaluation which can make full use of the computing resources. The experimental results demonstrate that this method can reduce the simulation time effectively while achieving better optimization results. Compared with the Multi-objective Acquisition function Ensemble (MACE) and the weighted expected improvement based Bayesian optimization (WEIBO), our proposed approach can accelerate the optimization process by up to $3 \times$ and $27 \times$.

Knee osteoarthritis (OA) is a chronic disease that considerably reduces patients' quality of life. Preventive therapies require early detection and lifetime monitoring of OA progression. In the clinical environment, the severity of OA is classified by the Kellgren and Lawrence (KL) grading system, ranging from KL-0 to KL-4. Recently, deep learning methods were applied to OA severity assessment to improve accuracy and efficiency. However, this task is still challenging due to the ambiguity between adjacent grades, especially in early-stage OA. Low confident samples, which are less representative than the typical ones, undermine the training process. Targeting the uncertainty in the OA dataset, we propose a novel learning scheme that dynamically separates the data into two sets according to their reliability. Besides, we design a hybrid loss function to help CNN learn from the two sets accordingly. With the proposed approach, we emphasize the typical samples and control the impacts of low confident cases. Experiments are conducted in a five-fold manner on five-class task and early-stage OA task. Our method achieves a mean accuracy of 70.13% on the five-class OA assessment task, which outperforms all other state-of-art methods. Despite early-stage OA detection still benefiting from the human intervention of lesion region selection, our approach achieves superior performance on the KL-0 vs. KL-2 task. Moreover, we design an experiment to validate large-scale automatic data refining during training. The result verifies the ability to characterize low confidence samples. The dataset used in this paper was obtained from the Osteoarthritis Initiative.

Automated analog circuit design is promising for increasing the design productivity and narrowing the time-tomarket, but is facing the bottleneck of tremendous design complexity. In this paper, a simulation-based optimization approach named smart-multiple starting point (MSP) is proposed for analog circuit synthesis. The proposed smart-MSP is based on the framework of MSP optimization, which is shown to be much more efficient than other global optimization methods like simulated annealing, genetic algorithm, particle swarm optimization, etc. Efficient techniques including heuristic-biased starting point selection, sparse regression and probabilistic TABU are developed in smart-MSP and make the algorithm quite smart in a way that the overall optimization process is self-adaptive by learning from the previous local searches and can efficiently produce optimal results to approximate the global optimum. Experiments have demonstrated that the proposed smart-MSP is 2.6-12.5× faster than the original MSP method, and is 1.3-2100× faster than other state-of-the-art methods.

Random region covering is a global optimization technique that explores the landscape by introducing multiple random starting points to initiate the local optimization solvers. This study applies the random region covering technique to circuit design automation and proposes a theory to explain why this technique is efficient at searching for the global optimum. In addition to analyzing the efficiency of the random region covering algorithm, the theory gives a probability-based estimation of the goodness of the optimization result. To enhance the efficiency of the random region covering technique, this work evaluates the boundary of top performance regions and proposes a modified random region covering method that only performs the global optimization on the top design region. The results from a large number of mathematical experiments verify the proposed methodology. The optimized designs of a class-E power amplifier and a wide load range operational amplifier outperform both manual designs and other state-of-the-art optimization techniques.

Optimization-simulation loop-based method is popular and efficient in design migration/reuse automation. However, it is only restricted to be used in block-level due to the complexity of current mixed-signal system. This paper presents a hierarchical methodology for efficiently migrating mixed-signal circuit design from one technology node to another, while keeping the same circuit and layout topologies. It utilizes two stages of optimization processes to automatically resize and refine device dimensions in target technology. In the first stage, to avoid the costly simulation time without scarifying systematical functionality, only one block is represented in transistor level (TL), while other blocks are replaced with behavioral models. The multistart global optimization technique is applied to resize the TL block in systematic connection. This stage provides a good initial point for next system-level refinement. Moreover, for obtaining a process and parasitic closure solution, both parasitic and process variation effects are explored and used to constrain the schematic migration. A representative mixed-signal system, charge-pump phase-locked loop, is used to validate the proposed methodology. The experimental results show that the proposed methodology efficiently generates quality designs in target technology with much less simulation iterations, when comparing with recent available approaches.