Sampling signals with a high dynamic range (DR) poses significant challenges in analog-to-digital conversion (ADC), where the DR of the ADC must exceed that of the input signal to prevent information loss. Modulo sampling offers a promising solution to this problem by reducing the DR of the signal prior to sampling. In this paper, we address the modulo recovery problem in scenarios where the folding parameter is unknown and potentially time-varying, motivated by practical hardware limitations that make it difficult to maintain a constant and precise folding parameter. We provide a theoretical guarantee for the unique recovery of band-limited (BL) signals from modulo samples without requiring knowledge of the folding parameter. Additionally, we develop a robust recovery algorithm specifically for scenarios with a constant but unknown folding parameter. The algorithm’s performance is evaluated through simulations under various conditions, including different oversampling rates and noise levels. The results demonstrate that our method achieves high accuracy in signal recovery, even in challenging environments.

A fully integrated hardware design of the universal maximum likelihood Guessing Random Additive Noise Decoding (GRAND) algorithm implemented in 40 nm CMOS is presented. It is shown how this integrated hard-detection decoder, which is designed to process component codes of up to 128 bits in length, can be extended to efficiently decode product codes as long as 16,384 bits using the Iterative GRAND (IGRAND) algorithm. Pipelined stages provide throughput gain and dynamic energy savings when channel noise conditions improve. The chip allows for decoding product codes with two distinct component codes due to its ability to interleave between two codebooks without any switch-over time. Measurements demonstrate the decoder’s accuracy and efficiency in decoding a broad selection of product codes, including the capacity-achieving random linear product codes. The chip consumes an average energy of 30.6 pJ/b with a latency of 1.04 μs when decoding the BCH(127,106,7) component code at 68 MHz from 1.1 V at a bit flip probability of 10-5. Using a single chip to decode a BCH(127,106,7)2product code which results in 16,129-bit code of rate 0.68, we demonstrate an average energy consumption of 61.2 pJ/b with an average latency of 265 μs for the same operating conditions.

Fully Homomorphic Encryption (FHE) offers protection to private data on third-party cloud servers by allowing computations on the data in encrypted form. To support general-purpose encrypted computations, all existing FHE schemes require an expensive operation known as "bootstrapping". Unfortunately, the computation cost and the memory bandwidth required for bootstrapping add significant overhead to FHE-based computations, limiting the practical use of FHE.In this work, we propose FAB, an FPGA-based accelerator for bootstrappable FHE. Prior FPGA-based FHE accelerators have proposed hardware acceleration of basic FHE primitives for impractical parameter sets without support for bootstrapping. FAB, for the first time ever, accelerates bootstrapping (along with basic FHE primitives) on an FPGA for a secure and practical parameter set. The key contribution of this work is the architecture of a balanced FAB design, which is not memory bound. In our design, we leverage recent algorithms for bootstrapping while being cognizant of the compute and memory constraints of our FPGA. In addition, we use a minimal number of functional units for computing, operate at a low frequency, leverage high data rates to and from main memory, utilize the limited on-chip memory effectively, and perform careful operation scheduling.We evaluate FAB using a single Xilinx Alveo U280 FPGA and by scaling it to a multi-FPGA system consisting of eight such FPGAs. For bootstrapping a fully-packed ciphertext, while operating at 300MHz, FAB outperforms existing state-of-the-art CPU and GPU implementations by 213× and 1.5× respectively. Our target FHE application is training a logistic regression model over encrypted data. For logistic regression model training scaled to 8 FPGAs on the cloud, FAB outperforms a CPU and GPU by 456× and 9.5× respectively, providing practical performance at a fraction of the ASIC design cost.

Random jammers that overpower transmitted signals are a practical concern for many wireless communication protocols. As such, wireless receivers must be able to cope with standard channel noise and jamming (intentional or unintentional). To address this challenge, we propose a novel method to augment the resilience of the recent family of universal error-correcting GRAND algorithms. This method, called Erasure Decoding by Gaussian Elimination (EDGE), impacts the syndrome check block and is applicable to any variant of GRAND. We show that the proposed EDGE method naturally reverts to the original syndrome check function in the absence of erasures caused by jamming. We demonstrate this by implementing and evaluating GRAND-EDGE and ORBGRAND-EDGE. Simulation results, using a Random Linear Code (RLC) with a code rate of 105/128, show that the EDGE variants lower both the Block Error Rate (BLER) and the computational complexity by up to five order of magnitude compared to the original GRAND and ORBGRAND algorithms. We further compare ORBGRAND-EDGE to Ordered Statistics Decoding (OSD), and demonstrate an improvement of up to three orders of magnitude in the BLER.

For communications subject to correlated channel effects, noise recycling has recently been shown to enhance channel capacity with receiver-side-only changes. Using a taped-out chip, in a hard-detection scenario with guessing random additive noise decoding (GRAND), noise recycling has been established to both increase decoding accuracy and decrease decoding energy in single communication channels that employ interleavers. This paper presents results for the related soft-detection scenario by investigating noise recycling with an in-silicon realization of Ordered Reliability Bits Guessing Random Additive Noise Decoding (ORBGRAND). Measurements demonstrate that noise recycling leads to a significant reduction in the block error rate (BLER) and substantial improvements in latency and energy consumption by reducing the number of queries required for decoding. We also discuss dynamic lead channel selection for the soft detection scenario and show the importance of lead channel on overall decoding performance.

This work presents an interactive real-time demonstration of the first-integrated universal soft-detection decoder with an ultra-low energy consumption of 0.76pJ/bit and the lowest power of 4.9mW using Ordered Reliability Bits Guessing Random Additive Noise Decoding (ORBGRAND) [1]. The chip has a reconfigurable code length of 32 to 256 bits. The chip’s universality is demonstrated by decoding multimedia messages using different codebooks through an interactive Graphics User Interface (GUI). It is shown that the chip’s performance is independent of the codebook used and dynamically adapts to the channel noise conditions where lower energy is consumed as the Signal-to-Noise Ratio (SNR) of the channel improves.

Multiple-input multiple-output (MIMO) systems utilize multiple antennas and signal acquisition chains, facilitating multi-user communications with increased spectral efficiency and better coverage via beamforming. MIMO systems are typically costly to implement and consume high power. A commonly used method to reduce the cost of MIMO receivers is to design hybrid analog/digital beamforming (HBF), which reduces the number of RF chains. However, the added analog circuitry involves active components whose consumed power may surpass that saved in RF chain reduction. An additional method to realize power-efficient MIMO systems is to use low-resolution analog-to-digital converters (ADCs), however, compromising signal recovery accuracy. In this work, we propose a power-efficient hybrid MIMO receiver with dedicated beamforming to mitigate spatial interferers in congested environments, utilizing low-quantization rate ADCs, jointly optimizing the analog and digital processing using task-specific quantization techniques. We present an efficient analog pre-processing hardware architecture utilizing sparse low-resolution vector modulators to reduce analog processing power while maintaining recovery accuracy. Supported by numerical simulations and power analysis, our power-efficient MIMO receiver achieves comparable signal recovery performance to power-hungry fully-digital MIMO receivers using high-resolution ADCs. Furthermore, our receiver outperforms the task-agnostic HBF receivers with low-quantization rate ADCs in recovery accuracy at lower power.

Noise recycling is a recently proposed method that significantly enhances decoding performance when used for orthogonal channels impacted by correlated noise with only receiver side changes. In this paper, we establish that noise recycling can be applied in a single communication channel that is subject to temporally correlated noise by leveraging a standard matrix interleaver to create the effect of orthogonal channels. The proposed interleaved noise recycling technique works with any code, requires no sender-side alterations, and only minor changes to the receiver architecture. In a hard-detection scenario, we demonstrate noise recycling can enable an accurate estimate of continuous realization of noise without using any soft information, resulting in a gain of more than 2 dB in Block Error Rate (BLER). We use the first hardware implementation of Guessing Random Additive Noise Decoding (GRAND), a universal noise-centric decoder, to illustrate the advantages of noise recycling in hardware performance. At a correlation coefficient of 0.75, Eb/N0of 4 dB, a maximum of 36× decoding energy savings with a 12× reduction in latency is achieved using a BCH(127,113) code when GRAND is equipped with the proposed noise recycling.

Phase-based ranging has been widely deployed in proximity detection scenarios including security-critical applications due to their low implementation complexity on existing transceivers. In this work, the security of multi-carrier phase-based ranging systems in a multipath propagation environment is investigated. We present a threat model that can successfully target any decreasing distance in different multipath environmental conditions rendering the phase-based ranging method insecure. We assess the feasibility of attacks in various attack scenarios through simulations using a multipath channel and demonstrate a simplified version of the attacker model implemented in hardware. We show that the attacker can spoof the measured distance to less than one meter when the devices are separated by 30 meters. The evaluation of possible countermeasures and their limitations for different threat models is performed.

This work provides an analysis of dual-factor authentication protocol for securing low-power medical devices. The dual-factor protocol incorporates voluntary physical action-based authentication in addition to traditional cryptographic methods for adding an extra layer of security. Along with touch signals, we propose and analyze the use of electromyographic (EMG) signals obtained from hand gestures for the second factor authentication. We demonstrate the feasibility of touch and EMG signals for dual-factor authentication by prototyping the medical device using off-the-shelf components. We also develop energy models for all these protocols, and analyze their overheads compared to traditional single-factor cryptographic authentication.

We introduce Iterative GRAND (IGRAND), a universal product code decoder that applies iterative bounded distance decoding and decodes component codes using code-agnostic Guessing Random Additive Noise Decoding (GRAND). We empirically determine its accuracy and, based on GRAND hardware measurements, its complexity, showing gains over alternative algorithms. We prove that the class of product codes with random linear component codes, which IGRAND is capable of decoding, are capacity-achieving in hard-decision channels.

Silicon-based terahertz (THz) integrated circuits (ICs) have made rapid progress over the past decade. The demonstrated basic component performance, as well as the maturity of design tools and methodologies, have made it possible to build high-complexity THz integrated systems. Such implementations are undoubtedly highly attractive due to their low cost and high integration capability; however, their unique characteristics, both advantageous and disadvantageous, also call for research investigations into unconventional systematic architectures and novel THz applications. In this paper, we review the current status and future trend of silicon-based THz ICs, with the focus on state-of-the-art THz microsystems for emerging sensing and communication applications in the last few years, such as high-resolution imaging, high medium/long-term stability time keeping, high-speed wireline/wireless communications, and miniaturization of RF tags, as well as THz packaging technologies.

Next-generation (Next-G) wireless terminals need to sense their ambient and adapt to the diverse deployment scenario requirements on the fly while leveraging technology scaling. Several key circuit and system innovations are required to make the realization of this vision possible. We discuss how compressed sampling can be exploited to design a rapid, GHz-wide and energy-efficient interferer detector using a quadrature analog-to-information converter. A family of field-programmable receiver front ends demonstrating two linearity enhancement techniques including interferer-reflecting loops and hybrid Class-AB-C low noise transconductors is discussed. The technology scalable and out-of-band blocker robust switched-capacitor RF front end is then presented.